CAT661 Datasheet, PDF (3/16 Pages) Catalyst Semiconductor – High Frequency 100mA CMOS Charge Pump, Inverter/Doubler

CAT661
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
V+ to GND
6
V
Input Voltage (Pins 1, 6 and 7)
−0.3 to (V+ + 0.3)
V
BOOST/FC and OSC Input Voltage
The least negative of (Out − 0.3 V) or
V
(V+ − 6 V) to (V+ + 0.3 V)
Output Short−circuit Duration to GND
1
sec.
(OUT may be shorted to GND for 1 sec without damage but shorting OUT
to V+ should be avoided.)
Continuous Power Dissipation (T_A = 70°C)
Plastic DIP
SO
TDFN
730
mW
500
mW
1
W
Storage Temperature
−65 to +160
°C
Lead Soldering Temperature (10 sec)
300
°C
ESD Rating − Human Body Model
2000
V
Operating Ambient Temperature Range
−40 to +85
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
NOTE: T_A = Ambient Temperature
Table 3. ELECTRICAL CHARACTERISTICS (V+ = 5 V, C1 = C2 = 100 mF, Boost/FC = Open, C_OSC = 0 pF, and Test Circuit is
Figure 3 unless otherwise noted. Temperature is T_A = T_AMIN to T_AMAX unless otherwise noted.)
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Supply Voltage
Supply Current
VS
Inverter: LV = Open, R_L = 1 kW
Inverter: LV = GND, R_L = 1 kW
Doubler: LV = OUT, R_L = 1 kW
IS
BOOST/FC = open, LV = Open
3.0
5.5
V
1.5
5.5
2.5
5.5
0.2
0.5
mA
BOOST/FC = V+, LV = Open
1
3
Output Current
IOUT OUT is more negative than −4 V
100
mA
Output Resistance
RO
C1 = C2 = 10 mF
BOOST/FC = V+ (C1, C2 ESR ≤ 0.5 W)
3.5
10
W
C1 = C2 = 100 mF (Note 2)
3.5
10
Oscillator Frequency
(Note 3)
FOSC
BOOST/FC = Open
BOOST/FC = V+
10
25
kHz
80
135
OSC Input Current
IOSC
BOOST/FC = Open
BOOST/FC = V+
±2
mA
±10
Power Efficiency
PE
R_L = 1 kW connected between V+ and OUT,
96
98
%
T_A = 25°C (Doubler)
R_L = 500 W connected between GND and OUT,
92
96
T_A = 25°C (Inverter)
I_L = 100 mA to GND, T_A = 25°C (Inverter)
88
Voltage Conversion
Efficiency
VEFF No load, T_A = 25°C
99
99.9
%
1. In Figure 3, test circuit electrolytic capacitors C1 and C2 are 100 mF and have 0.2 W maximum ESR. Higher ESR levels may reduce efficiency
and output voltage.
2. The output resistance is a combination of the internal switch resistance and the external capacitor ESR. For maximum voltage and efficiency
keep external capacitor ESR under 0.2 W.
3. FOSC is tested with C_OSC = 100 pF to minimize test fixture loading. The test is correlated back to C_OSC = 0 pF to simulate the capacitance
at OSC when the device is inserted into a test socket without an external C_OSC.
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