CAT5411 Datasheet, PDF(3/16 Page) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and SPI Interface

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CAT5411 Datasheet, PDF (3/16 Pages) Catalyst Semiconductor – Dual Digitally Programmable Potentiometers (DPP) with 64 Taps and SPI Interface

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DEVICE OPERATION

The CAT5411 is two resistor arrays integrated with

SPI serial interface logic, two 6-bit wiper control

registers and eight 6-bit, non-volatile memory data

registers. Each resistor array contains 63 separate

resistive elements connected in series. The physical

ends of each array are equivalent to the fixed

terminals of a mechanical potentiometer (RH and RL).

RH and RL are symmetrical and may be interchanged.

The tap positions between and at the ends of the

series resistors are connected to the output wiper

terminals (RW) by a CMOS transistor switch. Only one

tap point for each potentiometer is connected to its

wiper terminal at a time and is determined by the

value of the wiper control register. Data can be read

or written to the wiper control registers or the non-

volatile memory data registers via the SPI bus.

Additional instructions allow data to be transferred

between the wiper control registers and each

respective potentiometer's non-volatile data registers.

Also, the device can be instructed to operate in an

"increment/decrement" mode.

CAT5411

SERIAL BUS PROTOCOL

The CAT5041 supports the SPI bus data transmission

protocol. The synchronous Serial Peripheral Interface

(SPI) helps the CAT5411 to interface directly with

many of today's popular microcontrollers.

The CAT5041 contains an 8-bit instruction register.

The instruction set and the operation codes are

detailed in the instruction set table 3.

After the device is selected with Â¯CÂ¯SÂ¯ going low the first

byte will be received. The part is accessed via the SI

pin, with data being clocked in on the rising edge of

SCK. The first byte contains one of the six op-codes

that define the operation to be performed.

RELIABILITY CHARACTERISTICS

Over recommended operating conditions unless otherwise stated.

Symbol

NEND (1)

TDR(1)

VZAP(1)

ILTH(1)

Parameter

Endurance

Data Retention

ESD Susceptibility

Latch-Up

Reference Test Method

Min

Typ Max

Units

MIL-STD-883, Test Method 1033 1,000,000

Cycles/Byte

MIL-STD-883, Test Method 1008

100

Years

MIL-STD-883, Test Method 3015

2000

Volts

JEDEC Standard 17

100

Notes:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

Characteristics subject to change without notice

Doc. No. MD-2114 Rev. L

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