CAT28F512 Datasheet, PDF (3/16 Pages) Catalyst Semiconductor – 512K-Bit CMOS Flash Memory

CAT28F512
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –45°C to +130°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground⁽¹⁾ ........... –2.0V to +VCC + 2.0V
Voltage on Pin A9 with
Respect to Ground⁽¹⁾ ................... –2.0V to +13.5V
VPP with Respect to Ground
during Program/Erase⁽¹⁾ .............. –2.0V to +14.0V
VCC with Respect to Ground⁽¹⁾ ............ –2.0V to +7.0V
Package Power Dissipation
Capability (TA = 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current⁽²⁾ ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
RELIABILITY CHARACTERISTICS
Symbol
N_END(3)
T_DR(3)
V_ZAP(3)
I_LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE T_A = 25°C, f = 1.0 MHz
Symbol
C_IN(3)
C_OUT(3)
C_VPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
V_PP Supply Capacitance
Limits
Min
Max.
6
10
25
Units
pF
pF
pF
Conditions
V_IN = 0V
V_OUT = 0V
V_PP = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V_CC +0.5V, which may overshoot to V_CC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V_CC +1V.
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
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Doc. No. MD-1084, Rev. K