CAT25320 Datasheet, PDF (3/16 Pages) Catalyst Semiconductor – 32-Kb SPI Serial CMOS EEPROM

CAT25320
Table 5. A.C. CHARACTERISTICS (T_A = −40°C to +85°C (Industrial) and T_A = −40°C to +125°C (Extended).) (Notes 4, 7)
V_CC = 1.8 V − 5.5 V / −405C to +855C
V_CC = 2.5 V − 5.5 V / −405C to +1255C
V_CC = 2.5 V − 5.5 V
−405C to +855C
Symbol
Parameter
Min
Max
Min
Max
Units
f_SCK
Clock Frequency
DC
5
DC
t_SU
Data Setup Time
40
20
t_H
Data Hold Time
40
20
t_WH
SCK High Time
75
40
t_WL
SCK Low Time
75
40
t_LZ
HOLD to Output Low Z
50
t_RI (Note 5)
Input Rise Time
2
t_FI (Note 5)
Input Fall Time
2
t_HD
HOLD Setup Time
0
0
t_CD
HOLD Hold Time
10
10
t_V
Output Valid from Clock Low
75
t_HO
Output Hold Time
0
0
t_DIS
Output Disable Time
50
t_HZ
HOLD to Output High Z
100
t_CS
CS High Time
50
20
t_CSS
CS Setup Time
20
15
t_CSH
CS Hold Time
30
20
t_CNS
CS Inactive Setup Time
50
15
t_CNH
CS Inactive Hold Time
50
15
t_WPS
WP Setup Time
10
10
t_WPH
WP Hold Time
100
60
t_WC (Note 6)
Write Cycle Time
5
4. AC Test Conditions:
Input Pulse Voltages: 0.3 V_CC to 0.7 V_CC
Input rise and fall times: ≤ 10 ns
Input and output reference voltages: 0.5 V_CC
Output load: current source I_{OL max}/I_{OH max}; C_L = 50 pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
10
MHz
ns
ns
ns
ns
25
ns
2
ms
2
ms
ns
ns
40
ns
ns
20
ns
25
ns
ns
ns
ns
ns
ns
ns
ns
5
ms
6. t_WC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
7. All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t_CSH timing specification is valid
for die revision C and higher. The die revision C is identified by letter “C” or a dedicated marking code on top of the package. For
previous product revision (Rev. B) the t_CSH is defined relative to the negative clock edge (please refer to data sheet
Doc. No. MD−1111 Rev. I)
Table 6. POWER−UP TIMING (Notes 5, 8)
Symbol
Parameter
Max
t_PUR
Power−up to Read Operation
1
t_PUW
Power−up to Write Operation
1
8. t_PUR and t_PUW are the delays required from the time V_CC is stable until the specified operation can be initiated.
Units
ms
ms
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