CAT24C512_15 Datasheet, PDF (3/17 Pages) ON Semiconductor – 512 Kb I2C CMOS Serial EEPROM

CAT24C512
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Ratings
–65 to +150
Units
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V_CC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V_CC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
N_END (Notes 3, 4)
Endurance
1,000,000
Program/Erase Cycles
T_DR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V_CC = 5 V, 25°C.
4. The device uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes. Therefore, when a single byte
has to be written, 4 bytes (including the ECC bits) are re-programmed. It is recommended to write by multiple of 4 bytes in order to benefit
from the maximum number of write cycles.
Table 3. D.C. OPERATING CHARACTERISTICS
V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C and V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Test Conditions
Min
Max
Units
I_CCR
Read Current
Read, f_SCL = 400 kHz/1 MHz
1
mA
I_CCW
Write Current
V_CC = 1.8 V
1.8
mA
V_CC = 5.5 V
2.5
I_SB
Standby Current
All I/O Pins at GND or V_CC
T_A = −40°C to +85°C
2
mA
T_A = −40°C to +125°C
5
I_L
I/O Pin Leakage
Pin at GND or V_CC
T_A = −40°C to +85°C
1
mA
T_A = −40°C to +125°C
2
V_IL1
Input Low Voltage
2.5 V ≤ V_CC ≤ 5.5 V
−0.5
0.3 V_CC
V
V_IL2
Input Low Voltage
1.8 V ≤ V_CC < 2.5 V
−0.5
0.25 V_CC
V
V_IH1
Input High Voltage
2.5 V ≤ V_CC ≤ 5.5 V
0.7 V_CC
V_CC + 0.5
V
V_IH2
Input High Voltage
1.8 V ≤ V_CC < 2.5 V
0.75 V_CC
V_CC + 0.5
V
V_OL1
Output Low Voltage
V_CC ≥ 2.5 V, I_OL = 3.0 mA
0.4
V
V_OL2
Output Low Voltage
V_CC < 2.5 V, I_OL = 1.0 mA
0.2
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C and V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 5)
SDA I/O Pin Capacitance
V_IN = 0 V
8
pF
C_IN (Note 5)
Input Capacitance (other pins)
V_IN = 0 V
6
pF
I_WP, I_A (Note 6)
WP Input Current, Address Input
Current (A₀, A₁, A₂)
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.3 V
75
mA
50
V_IN < V_IH, V_CC = 1.8 V
25
V_IN > V_IH
2
5. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
6. When not driven, the WP, A₀, A₁, A₂ pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
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