CAT24C44J Datasheet, PDF (3/9 Pages) ON Semiconductor – 256-Bit Serial Nonvolatile CMOS Static RAM

CAT24C44
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground⁽²⁾ ............. –2.0 to +VCC +2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current⁽³⁾ ........................ 100 mA
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation
of the device at these or any other conditions outside of
those listed in the operational sections of this specifica-
tion is not implied. Exposure to any absolute maximum
rating for extended periods may affect device perfor-
mance and reliability.
RELIABILITY CHARACTERISTICS
Symbol
Parameter
NEND(1)
TDR(1)
V_ZAP(1)
I_LTH(1)(4)
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
100,000
10
2000
100
Typ.
Max.
Units
Cycles/Byte
Years
Volts
mA
D.C. OPERATING CHARACTERISTICS
V_CC = 5V ±10%, unless otherwise specified.
Limits
Symbol
Parameter
Min. Typ. Max. Unit
ICCO Current Consumption (Operating)
3
mA
ISB
Current Consumption (Standby)
ILI
Input Current
ILO
Output Leakage Current
VIH
High Level Input Voltage
2
VIL
Low Level Input Voltage
0
VOH High Level Output Voltage
2.4
VOL Low Level Output Voltage
30 µA
2
µA
10 µA
VCC
V
0.8
V
V
0.4
V
Conditions
Inputs = 5.5V, TA = 0°C
All Outputs Unloaded
CE = VIL
0 ≤ VIN ≤ 5.5V
0 ≤ VOUT ≤ 5.5V
IOH = –2mA
IOL = 4.2mA
CAPACITANCE T_A = 25°C, f = 1.0 MHz, V_CC = 5V
Symbol
Parameter
Max.
Unit
Conditions
CI/O(1)
CIN(1)
Input/Output Capacitance
Input Capacitance
10
pF
6
pF
VI/O = 0V
VIN = 0V
Note:
(1) These parameter are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(2) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns.
Maximum DC voltage on output pins is V_CC +0.5V, which may overshoot to V_CC +2.0V for periods of less than 20 ns.
(3) Output shorted for no more than one second. No more than one output shorted at a time.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V_CC +1V.
© 2008 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-1083, Rev. T