CAT24C256YI-G Datasheet, PDF (3/18 Pages) ON Semiconductor – 256 kb I2C CMOS Serial EEPROM

CAT24C256
Table 5. D.C. OPERATING CHARACTERISTICS − New Product (Rev E) (Note 7)
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C and V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
Min
Max
I_CCR
I_CCW
I_SB
I_L
V_IL1
V_IL2
V_IH1
V_IH2
V_OL1
V_OL2
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
Output Low Voltage
Read, f_SCL = 400 kHz/1 MHz
All I/O Pins at GND or V_CC
Pin at GND or V_CC
2.5 V ≤ V_CC ≤ 5.5 V
1.8 V ≤ V_CC < 2.5 V
2.5 V ≤ V_CC ≤ 5.5 V
1.8 V ≤ V_CC < 2.5 V
V_CC ≥ 2.5 V, I_OL = 3.0 mA
V_CC < 2.5 V, I_OL = 1.0 mA
T_A = −40°C to +85°C
T_A = −40°C to +125°C
T_A = −40°C to +85°C
T_A = −40°C to +125°C
−0.5
−0.5
0.7 V_CC
0.75 V_CC
1
3
2
5
1
2
0.3 V_CC
0.25 V_CC
V_CC + 0.5
V_CC + 0.5
0.4
0.2
Units
mA
mA
mA
mA
V
V
V
V
V
V
Table 6. PIN IMPEDANCE CHARACTERISTICS − New Product (Rev E) (Note 7)
(V_CC = 1.8 V to 5.5 V, T_A = −40°C to +85°C and V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 8)
SDA I/O Pin Capacitance
V_IN = 0 V
8
pF
C_IN (Note 8)
Input Capacitance (other pins)
V_IN = 0 V
6
pF
I_WP, I_A (Note 9)
WP Input Current, Address Input
Current (A₀, A₁, A₂)
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.3 V
75
mA
50
V_IN < V_IH, V_CC = 1.8 V
25
V_IN > V_IH
2
7. The new product Rev E is identified by letter “E” or a dedicated marking code on top of the package.
8. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
9. When not driven, the WP, A₀, A₁, A₂ pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
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