AND8039 Datasheet, PDF (3/12 Pages) ON Semiconductor – The One-Transistor Forward Converter

AND8039/D
In the MKS system (Europe and elsewhere)
Npri [ (Vin(nom))ń4fB _max Ac
(eq. 2B)
where: B_max is in Teslas (webers/m²)
A_c is the core crossectional area in m²
This should be viewed as a nominal–minimum turns–count
since adding more turns lowers the operating flux density,
which may be counter–intuitive the average electric–based
engineer.
The reset winding is identical in turns to the primary
winding and usually about 3–4 wire gauges smaller than that
of the primary winding. It is phased oppositely from the
primary so that it can discharge the magnetization energy
when the power switch is off.
The secondary turns needed for this application is found
by realizing that the secondary voltage must provide an
output waveform that will have a volt–time average that will
create the proper output voltage when presented to the L–C
filter. In other words, (DC_maxV_out(min)) plus the forward
voltage drop of the output rectifier must be greater than the
DC output voltage. This can be done by:
N _sec [ 1.1 Npri (Vout ) Vfwd)ńVin(min) DC _max (eq. 3)
where:
DC_max is the maximum duty cycle of the system
(<0.5)
V_fwd is the nominal forward voltage drop of the
rectifier.
The 1.1 factor provides a 10 percent margin in the supply’s
low voltage dropout point and also provides margin for
other variations in the circuit. This secondary should be the
main output which would then serve as the reference
winding for all of the other secondary windings. One
should round the result up to the next integer turn.
When determining any additional secondary winding, one
must account for each of the forward voltage drops of their
respective rectifiers. This can be done by:
Nsec(n) [ Nsec(1) (Vout(n) ) Vfwd(n))ń(Vsec(1)
) Vfwd(1))
(eq. 4)
The accuracy of each of the output voltages must now be
considered. Some variation can be gotten by changing the
output rectifier technology, otherwise the turns can be
adjusted by raising the reference secondary winding by a
turn and adjusting the other windings. This is an iterative
process done until the output voltages are within an
acceptable tolerance and all of the windings are integer
turns.
This design example only has one output voltage. The
auxiliary winding which provides power to the control IC,
need not be regulated or accurate. It needs to only exceed the
low voltage inhibit limit of the UC3845 which is 8.0 V at the
low input voltage. Peak rectifying the auxiliary winding in
the forward conduction mode, yields a winding with 3.5
turns. Lets round up to 4 and add a series resistor (about 100
ohms) and a 18 V zener diode across the auxiliary voltage
filter capacitor to limit the maximum voltage. This will
protect the gate of the power MOSFET.
In this example, an EFD25 core will be used. The primary
turns were calculated to be 41 turns of a #24 AWG. The reset
winding will be 41T of #28 AWG. The secondary is 21 turns
of 2 stands of #22 AWG. The auxiliary winding will be 4
turns of #28 AWG. The primary and reset windings will be
wound first onto the bobbin. Next the auxiliary winding is
wound on top of these windings. Three layers of mylar tape
are applied to provide some degree of dielectric isolation
(not quite IEC), then the secondary winding will be applied
last. A last layer of tape is added to provide some protection
to the outer winding.
A cautious note must be now conveyed, this design
example is a non–isolated, high–voltage input power supply.
It is for example only and cannot be built for sale because it
does not meet the IEC (UL CSA or other) specifications for
dielectric isolation and for creepage (the distance along a
surface). To make this an off–line one transistor forward
converter, the input rectifier bridge, EMI filter, an
opto–isolated feedback circuit, an opto–isolated feedback
circuit and the transformer would have to be built to IEC
specifications.
Selection of the Power Semiconductors
Power Switch
In one–transistor forward converters, the power switch
will see twice the maximum input voltage plus any spikes
caused winding leakage inductance, and rectifier forward
and reverse characteristics. So the minimum V_DSS rating for
the power MOSFET is about:
VDSS(min) + 2 (Vin(max)) ) Vclamp(est) + 450 V
The minimum drain current rating should be greater than
just slightly less than slightly less than the maximum peak
current. This is 2.24 A.
Another major consideration, especially for surface
mount components, is the heat generated by the device. The
R_DS(ON) and the drive circuit have the greatest influence on
this. By over–rating the drain current, some reduction in heat
can be realized. This lessens the amount of PCB area needed
to keep the junction temperature of the MOSFET at a
reasonable temperature (about +40–+60°C). A reasonable
estimation of the maximum R_DS(on) assuming a heatsink
area of twice the minimum footprint area is:
RDS(on)(max) + 3.3 (DT)ń(Iin(av))2(Theta (jA)) (eq. 6)
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