NCP1605_12 Datasheet, PDF (29/32 Pages) ON Semiconductor – Enhanced, High Voltage and Efficient Standby Mode Power Factor Controller

NCP1605, NCP1605A, NCP1605B
Remarks:
The V_CONTROL signal does not necessarily reach its
clamp level (3.7 V) depending of the load and of the system
time constants. In particular, if the circuit starts operation
in light load and if the bulk capacitor is not too large, the
output voltage V_OUT generally exceeds the regulation level
while V_CONTROL keeps below its upper limit.
The output voltage exhibits a 100 or 120 Hz ripple (at
twice the line frequency). This ripple is also present in the
V_CONTROL voltage even if it is attenuated due to the
regulation low bandwidth. Like that of V_OUT, this ripple is
not represented in Figure 70, for the sake of the clarity.
V_CC
V_OUT
V_CONTROL
Flag1
V_CCON
V_CCINHIBIT
V_CCOFF
V_CCSTUP
V_CONTROL MAX = 3.7 V
V_OUT Regulation Level
These re−activations of “Flag1” result from V_OUT
100 or 120 Hz ripple (not represented here for the
sake of clarity)
Circuit State
OFF
pfcOK
Drive Output
Figure 70. Startup Phase in Normal Conditions
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