NCN5121_16 Datasheet, PDF (28/58 Pages) ON Semiconductor – Transceiver for KNX Twisted Pair Networks

NCN5121
SPI Interface
The SPI interface is selected by MODE1− and
MODE2−pin. The baudrate is determined by which
MODE−pin is pulled high (MODE1 pulled high = 125 kbps,
MODE2 pulled high = 500 kbps).
The SPI interface allows full duplex synchronous
communication between the device and the host controller.
The interface operates in Mode 0 (CPOL and CPHA = ‘0’)
meaning that the data is clocked out on the falling edge and
sampled on the rising edge. The LSB is transmitted first.
0
1
2
3
4
5
6
7
CSB
SCK
SDI
SDO
LSB
LSB
1
1
2
2
3
3
4
4
5
5
6
6
ÉÉ _MSB
ÉÉÉÉÉÉ _MSB
Figure 25. SPI Transfer
During SPI transmission, data is transmitted (shifted out
serially) on the SDO/TXD−pin and received (shifted in
serially) on the SDI/RXD−pin simultaneously. SCK/UC2 is
set as output and is used as the serial clock (SCK) to
synchronize shifting and sampling of the data on the SDI−
and SDO−pin. The speed of this clock signal is selectable
(see Table 9). The slave select line (CSB/UC1−pin) will go
low during each transmission allowing to selection the host
controller (CSB−pin is high when SPI is in idle state).
Shift Register
Control
SDO/TXD
SDI/RXD
SCK/UC2
CSB/UC1
MOSI
MISO
SCLK
SS
Shift Register
Control
NCN5121
Host Controller
Figure 26. SPI Master
In an SPI network only one SPI Master is allowed (in this
case NCN5121). To allow the host controller to
communicate with the device the TREQ−pin can be used
(Transmit Request). When NCN5121 detects a negative
edge on TREQ, the device will issue dummy transmission
of 8 bits which will result in a transmission of data byte from
the host controller to the device. See Figure 11 for details on
the timings. See Figure 13 for an SPI application example.
CSB
SCK
SDI
SDO
Dummy
0 123 45 67
D DDDD DDD
0 12 34
D DD DD
TREQ
Start dummy transmission
Figure 27. Transmission Request
www.onsemi.com
28