NCV7518_16 Datasheet, PDF (26/37 Pages) ON Semiconductor – Hex Low‐side MOSFET Pre‐driver

NCV7518, NCV7518A
APPLICATION GUIDELINES
General
Unused DRN_X inputs should be connected to V_LOAD to
prevent false open load faults. Unused parallel inputs should
be connected to GND and unused reset or enable inputs
should be connected to V_CC1 or GND respectively. The
user’s software should be designed to ignore fault
information for unused channels. For best shorted-load
detection accuracy, the external MOSFET source terminals
should be star-connected and the NCV7518’s GND pin, and
the lower resistor in the fault reference voltage divider
should be Kelvin connected to the star (see Figure 2).
Consideration of auto-retry fault recovery behavior is
necessary from a power dissipation viewpoint (for both the
NCV7518 and the MOSFETs) and also from an EMI
viewpoint.
Driver slew rate and turn-on/off symmetry can be adjusted
externally to the NCV7518 in each channel’s gate circuit by
the use of series resistors for slew control, or resistors and
diodes for symmetry. Any benefit of EMI reduction by this
method comes at the expense of increased switching losses
in the MOSFETs.
The channel fault blanking timers must be considered
when choosing external components (MOSFETs, slew
control resistors, etc.) to avoid false faults. Component
choices must ensure that gate circuit charge/discharge times
stay within the turn-on/turn-off blanking times.
The NCV7518 does not have integral drain-gate flyback
clamps. Self-clamped MOSFET products, such as
ON Semiconductor’s NIF9N05CL or NCV8440A devices,
are recommended when driving unclamped inductive loads.
This flexibility allows choice of MOSFET clamp voltages
suitable to each application.
Latch−off Recovery and PWM Operation
When a channel is latched off and the recovery method
chosen is the diagnostic pulse, the recovery attempt can be
blocked by a PWM or other signal transition at the channel’s
parallel INx input. The transition starts an ON or OFF
blanking timer which will prevent execution of a pulse
request if the request via SPI is received while the timer is
running.
This can be overcome by first sending Gx = 1 via SPI (i.e.
serial control) to override the channel’s INx input, reading
the diagnostic registers, then sending a pulse request. The
channel can then be released back to parallel control by
sending Gx = 0. Delays are added as necessary for the
appropriate blanking times between each step. Global
recovery may also be performed disabling then re−enabling
the device via the ENB input.
Auto−retry and OFF Pulse Interaction
A single hardware implementation serves as the global
auto−retry (t_FR) timer function for all channels and within
each channel the turn−on (t_BL(ON)) and turn−off (t_BL(OFF))
blanking timers are shared (single hardware
implementation) with t_BL(ON) time dominant. These same
blanking timers also generate the ON or OFF diagnostic
pulses.
If a channel configured for auto−retry is continuously
commanded ON and becomes faulted (SCB), it remains ON
and a turn−on blanking time is initiated every 8 ms for the
faulted channel and also for each non−faulted ON channel
configured for auto−retry. If a channel configured for
auto−retry is commanded OFF, it remains OFF and no
blanking timers are started.
When a diagnostic OFF pulse request is received just prior
to an auto−retry cycle, the channel’s t_BL(OFF) timer can be
interrupted by the auto−retry timer (t_BL(ON) blanking time
initiation). For example, a channel’s t_BL(OFF) timer is
programmed for 162 ms and an OFF pulse is requested and
begins execution, but before it can complete its timeout, the
auto−retry initiates a t_BL(ON) blanking time. Due to the
blanking timer sharing, the t_BL(OFF) timer does not complete
its timeout and the pulse request becomes locked out.
The number of locked−out channels depends on which
ones were programmed for auto−retry and which ones were
requesting an OFF−pulse within the described zone of
vulnerability. Further OFF pulse requests will fail to execute
for each locked−out channel.
This interaction can be avoided for channels operated in
a constant−on state by selecting the latch−off recovery mode
and emulating the auto−retry mode. This can be done by
sending a series of read status and diagnostic pulse execution
requests with appropriate delays on a scheduled (e.g. every
10 ms) basis. Global recovery may also be performed
disabling then re−enabling the device via the ENB input.
Parity Error Handling
The SPI input (SI) shift register is reset (forced to 0x00)
in case of an invalid frame resulting from either an incorrect
frame length or incorrect parity. The ‘live’ parity check
hardware implementation of the SI register content is
blocked during a frame by CSB. When CSB goes high and
the frame length is correct but parity is incorrect, parity
check inputs may change as the SI register is forced to 0x00
and register data may be affected. In the event a parity error
occurs it is recommended to refresh all of the device’s
configuration (write) registers. Register data is not affected
if the frame length is incorrect.
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