CS5308 Datasheet, PDF (26/31 Pages) ON Semiconductor – Two−Phase PWM Controller with Integrated Gate Drivers for VRM 8.5

CS5308
Design Example
Typical Design Requirements:
V_IN = 5.0 Vdc
V_OUT = 1.70 Vdc (nominal)
V_OUT,RIPPLE = 10 mV_PP max
VID Range: 1.050 Vdc − 1.825 Vdc
I_O,MAX = 28 A at full−load
I_OUT,LIM = 33 A min at 50°C (shutdown threshold)
dI_IN/dt = 0.1 A/ms max
f_SW = 335 kHz
h = 81% minimum
T_A,MAX = 60°C
T_J,MAX = 115°C
T_D,VTT = 2.5 ms (VTT_PGD delay time)
T_SS = 6.5 ms (Soft Start time)
DV_OUT at no−load (static) =
+45 mV from VID setting = 1.745 Vdc
DV_OUT at full−load (static) =
−45 mV from VID setting = 1.655 Vdc
DV_OUT at full−load (transient) =
-90 mV from VID setting = 1.610 Vdc
1. Output Capacitor Selection
First, choose a low−cost, low−ESR output capacitor such as
the Rubycon 6.3ZA1000M10X16: 6.3 V, 1000 mF, 1.65 A_RMS,
24 mW, 10 × 16 mm. Calculate the minimum number of
output capacitors:
NOUT,MIN
+
ESR
per
capacitor
@
DIO,MAX
DVO,MAX
(1)
+ 24 mW @ 28 Ań(1.745 V * 1.610 V)
+ 4.987 or 5 capacitors minimum (5000 mF)
2. Output Inductor Selection
Calculate the minimum output inductance at I_O,MAX
according to Equation 3 with ±20% inductor ripple current
(a = 0.20):
LoMIN
+
(VIN * VOUT) @ VOUT
(a @ IO,MAX @ VIN @ fSW)
(3)
+
(5 V * 1.655
(0.2 @ 28 A @ 5
V)
V
@ 1.655 V
@ 335 kHz)
+ 590 nH
To save cost, we choose the inexpensive T50-52 core
from Micrometals: 33 nH/N², 3.19 cm./turn. At 14 A per
phase the permeability of this core will be approximately
80% of the permeability at 0 A. Therefore, at 0 A we must
achieve at least 590 nH/0.8 or 738 nH. Using four turns
results in only 528 nH, so we must use five turns of #16AWG
bifilar (2 mW/ft.) to produce 825 nH. This inductor is
available as part number CTX22−15401 from Coiltronics.
Use Equation 4 to insure the output voltage ripple will
satisfy the design goal with the minimum number of
capacitors and the nominal output inductance:
VOUT,P_−P + (ESR per cap ń NOUT,MIN) @
(4)
NJ_{(VIN * #Phases @ VOUT) @ D ń (LoMIN @ fSW)}Nj
+ (24 mWń5) @
NJ_{(5.0 V * 2 @ 1.7 V) @ (1.7 Vń5.0 V)ń(825 nH @ 335 kHz)}Nj
+ (4.8 mW) @ {1.97 A}
+ 9.45 mV
The output voltage ripple will be decreased when output
capacitors are added to satisfy transient loading
requirements.
We will need the nominal and worst case inductor
resistances for subsequent calculations:
RL + 5 turns @ 3.19 cmńturn @ 0.03218 ftńcm @ 2 mWńft
+ 1.03 mW
The inductor resistance will be maximized when the
inductor is “hot” due to the load current and the ambient
temperature is high. Assuming a 40°C temperature rise of
the inductor at full−load and a 25°C ambient temperature
rise we can calculate:
RL,MAX + 1.03 mW @ [1 ) 0.39%ń°C @ (40°C ) 25°C)]
+ 1.29 mW
3. Input Capacitor Selection
Use Equation 5 to determine the average input current to
the converter:
IIN,AVG + IO,MAX @ Dńh
(5)
+ 28 A @ (1.655 Vń5.0 V)ń0.81 + 11.44 A
Next, use Equations 6 to 10:
DILo + (VIN * VOUT) @ Dń(Lo @ fSW)
+
(5
V
*
1.655
V)
@
(1.655
(825 nH
Vń5.0 V)
@ 335 kHz)
(10)
+ 4.00 App
ILo,MAX + IO,MAXń2 ) DILoń2
(8)
+ 28 Ań2 ) 4 Appń2 + 16 A
ILo,MIN + IO,MAXń2 * DILoń2
+ 28 Ań2 * 4 Appń2 + 12 A
(9)
IC,MAX + ILo,MAXńh * IIN,AVG
(6)
+ 16 Ań0.81 * 11.44 A + 8.3 A
IC,MIN + ILo,MINńh * IIN,AVG
(7)
+ 12 Ań0.81 * 11.44 A + 3.3 A
For the two−phase converter, the input capacitor(s) RMS
current is then (Note: D = 1.655 V/5 V = 0.331):
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