AX5243 Datasheet, PDF (25/65 Pages) ON Semiconductor – Advanced high performance ASK

Circuit Description 25
5.1. Voltage Regulators
The AX5243 uses an on-chip voltage regulator system to create stable supply voltages
for the internal circuitry from the primary supply VDD_IO. The I/O level of the digital
pins is VDD_IO.
Pins VDD_ANA are supplied for external decoupling of the power supply used for the on-
chip PA.
The voltage regulator system must be set into the appropriate state before receive or
transmit operations can be initiated. This is handled automatically when programming
the device modes via the PWRMODE register.
Register POWSTAT contains status bits that can be read to check if the regulated voltages
are ready (bit SVIO) or if VDD_IO has dropped below the brown-out level of 1.3V (bit
SSUM).
In power-down mode the core supply voltages for digital and analog functions are
switched off to minimize leakage power. Most register contents are preserved but access
to the FIFO is not possible and FIFO contents are lost. SPI access to registers is possible,
but at lower speed.
In deep-sleep mode all supply voltages are switched off. All digital and analog functions
are disabled. All register contents are lost. To leave deep-sleep mode the pin SEL has to
be pulled low. This will initiate startup and reset of the AX5243. Then the MISO line
should be polled, as it will be held low during initialization and will rise to high at the end
of the initialization, when the chip becomes ready for operation.
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AX5243