NCP1381 Datasheet, PDF (23/26 Pages) ON Semiconductor – Low−Standby High Performance PWM Controller

NCP1381
35
25
15
5.0
−5.0
6.5
4.5
2.5
500m
−1.5
14
10
6.0
2.0
−2.0
Plot2
V_CC
41.3m
41.8m
Plot3
P_ON Reset
41.3m
Plot1
41.8m
B_OK
42.4m
42.4m
42.9m
42.9m
43.5m
43.5m
41.3m
41.8m
42.4m
42.9m
43.5m
TIME (s)
The B_OK comes back in the upslope but the logic 2 waits until UVOL circuitry detects 15 V to restart the Control-
ler.
Figure 35.
8.50 18.0
6.50 14.0
15 V
V_CC
4.50 10.0
2.50 6.00
500m 2.00
V_OK
20.0m
60.0m
100m
TIME (s)
140m
180m
In short−circuit, the V_CC drops to VCC_latch and goes up to 15 V. The blue trace corresponds to the “ok to pulse” signal whose duration is
given by the fault timer (purposely reduced on this simulation). Should a VCC_OFF condition be detected, or a B_OK fault, the duration would
be accordingly truncated.
Figure 36.
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