NCP1360 Datasheet, PDF (23/29 Pages) ON Semiconductor – Low Power Offline Constant Current & Constant Voltage PWM Current-Mode Controller

NCP1360, NCP1365
Timeout
The ZCD block actually detects falling edges of the
auxiliary winding voltage applied to the ZCD pin. At
start−up or during other transient phases, the ZCD
comparator may be unable to detect such an event. Also, in
the case of extremely damped oscillations, the system may
not succeed in detecting all the valleys required by valley
lockout operation (VLO, see next section). In this condition,
the NCP1365 ensures continued operation by incorporating
a maximum timeout period that resets itself when a
demagnetization phase is properly detected. In case the
ringing signal is too weak or heavily damped, the timeout
signal supersedes the ZCD signal for the valley counter.
Figure 50 shows the timeout period generator circuit
schematic. The timeout duration, t_out, is set to 5.5 ms (typ.).
During startup, the output voltage is still low, leading to
long demagnetization phase, difficult to detect since the
auxiliary winding voltage is small as well. In this condition,
the t_out timeout is generally shorter than the inductor
demagnetization period and if used to restart a switching
cycle, it can cause continuous current mode (CCM)
operation for a few cycles until the voltage on the ZCD pin
is high enough for proper valleys detection. A longer
timeout period, t_outSS, (typically 44 ms) is therefore set
during soft−start to prevent CCM operation.
In VLO operation, the timeout occurrences are counted
instead of valleys when the drain−source voltage
oscillations are too damped to be detected. For instance,
assume the circuit must turn on at the third valley and the
ZCD ringing only enables the detection of:
• Valleys #1 to #2: the circuit generates a DRV pulse t_out
(steady−state timeout delay) after valley #2 detection.
• Valley #1: the timeout delay must run twice so that the
circuit generates a DRV pulse 10 ms (2*t_out typ.) after
valley #1 detection.
Valley LockOut (VLO) and Frequency Foldback (FF)
The operating frequency of a traditional Quasi−Resonant
(QR) flyback controller is inversely proportional to the
system load. In other words, a load reduction increases the
operating frequency. A maximum frequency clamp can be
useful to limit the operating frequency range. However,
when associated with a valley−switching circuit,
instabilities can arise because of the discrete frequency
jumps. The controller tends to hesitate between two valleys
and audible noise can be generated
To avoid this issue, the NCP1360/65 incorporates a
proprietary valley lockout circuitry which prevents
so−called valley jumping. Once a valley is selected, the
controller stays locked in this valley until the input level or
output power changes significantly. This technique extends
QR operation over a wider output power range while
maintaining good efficiency and naturally limiting the
maximum operating frequency.
The operating valley (from 1^st to 4^th valley) is determined
by the internal feedback level (FB node on Figure 4). As FB
voltage level decreases or increases, the valley comparators
toggle one after another to select the proper valley.
The decimal counter increases each time a valley is
detected. The activation of an “n” valley comparator blanks
the “n−1” or “n+1” valley comparator output depending if
V_FB decreases or increases, respectively. Figure 51 shows a
typical frequency characteristic obtained at low line in a
10 W charger.
Figure 51. Typical Switching Frequency versus Output Power Relationship in a 10 W Adapter
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