KAI-04022 Datasheet, PDF (23/43 Pages) ON Semiconductor – INTERLINE CCD IMAGE SENSOR

KAI−04022
TIMING
Table 12. TIMING REQUIREMENTS
Description
Symbol
Minimum
Nominal
Maximum
Unit
HCCD Delay
t_HD
1.3
1.5
10.0
ms
VCCD Transfer Time
t_VCCD
1.3
1.5
20.0
ms
Photodiode Transfer Time
t_V3rd
3.0
5.0
15.0
ms
VCCD Pedestal Time
t_3P
50.0
60.0
80.0
ms
VCCD Delay
t_3D
10.0
20.0
80.0
ms
Reset Pulse Time
t_R
2.5
5.0
−
ns
Shutter Pulse Time
t_S
3.0
4.0
10.0
ms
Shutter Pulse Delay
t_SD
1.0
1.5
10.0
ms
HCCD Clock Period (Note 1)
t_H
25.0
50.0
200.0
ns
VCCD Rise/Fall Time
t_VR
0.0
0.1
1.0
ms
Fast Dump Gate Delay
t_FD
0.5
−
−
ms
Vertical Clock Edge Alignment
t_VE
0.0
−
100
ns
1. For operation at the minimum HCCD clock period (40 MHz), the substrate voltage will need to be raised to limit the signal at the output to
20,000 electrons.
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