LV8044LPGEVK Datasheet, PDF (22/26 Pages) –

LV8044LP
Step Hold Function (D4 in the serial data)
When the hold bit in the serial data, D4 (100, *, D4, ***), is set to 1, the external step state at that time is held without
change as the internal step state.
Since the (external) step state is low at the timing of the step hold operation (1) in the figure, the internal step state is
held at the low level, and since the (external) step state is high at the timing of the step hold operation (1), the internal
step state is held at the high level.
When the hold data (D) is set to 0, the internal state is synchronized with the external step signal.
The output is held at the state at the point where the step hold was applied and after the step hold is released, it advances
with the timing of the next step input (rising edge).
As long as the IC is in the hold state, the position number does not advance even if external step pulses are applied.
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