AX8052F131_16 Datasheet, PDF (22/29 Pages) ON Semiconductor – SoC Ultra-Low Power RF-Microcontroller

AX8052F131
encoding is useful for PSK, because PSK transmissions
can be received either as transmitted or inverted, due to
the uncertainty of the initial phase. Differential
encoding / decoding removes this uncertainty.
• It can perform Manchester encoding. Manchester
encoding ensures that the modulation has no DC
content and enough transitions (changes from 0 to 1 and
from 1 to 0) for the demodulator bit timing recovery to
function correctly, but does so at a doubling of the data
rate.
• It can perform Spectral Shaping. Spectral shaping
removes DC content of the bit stream, ensures
transitions for the demodulator bit timing recovery, and
makes sure that the transmitted spectrum does not have
discrete lines even if the transmitted data is cyclic. It
does so without adding additional bits, i.e. without
changing the data rate. Spectral Shaping uses a self
synchronizing feedback shift register.
The encoder is programmed using the register
AX5031_ENCODING, details and recommendations on
usage are given in the AX5031 Programming Manual.
Framing and FIFO
Most radio systems today group data into packets. The
framing unit is responsible for converting these packets into
a bit−stream suitable for the modulator.
The Framing unit supports three different modes:
• HDLC
• Raw
• 802.15.4 compliant
The microcontroller communicates with the framing unit
through a 32 level × 10 bit FIFO. The FIFO decouples
microcontroller timing from the radio (modulator) timing.
The bottom 8 bits of the FIFO contain transmit data. The top
2 bits are used to convey meta information in HDLC and
802.15.4 modes. They are unused in Raw mode. The meta
information consists of packet begin / end information and
the result of CRC checks.
The FIFO can be operated in polled or interrupt driven
modes. In polled mode, the microcontroller must
periodically read the FIFO status register or the FIFO count
register to determine whether the FIFO needs servicing.
In interrupt mode EMPTY, NOT EMPTY, FULL, NOT
FULL and programmable level interrupts are provided.
Interrupts are acknowledged by removing the cause for the
interrupt, i.e. by emptying or filling the FIFO.
To lower the interrupt load on the microcontroller, one of
the DMA channels may be instructed to transfer data
between the transmitter FIFO and the XRAM memory. This
way, much larger buffers can be realized in XRAM, and
interrupts need only be serviced if the larger XRAM buffers
fill or empty.
HDLC Mode
NOTE: HDLC mode follows High−Level Data Link
Control (HDLC, ISO 13239) protocol.
HDLC Mode is the main framing mode of the
AX8052F131. In this mode, the AX8052F131 performs
automatic packet delimiting, and optional packet
correctness check by inserting and checking a cyclic
redundancy check (CRC) field.
The packet structure is given in the following table.
Table 17.
Flag
8 bit
Address
8 bit
Control
8 or 16 bit
Information
Variable length, 0 or more bits in multiples of 8
FCS
16 / 32 bit
Flag
8 bit
HDLC packets are delimited with flag sequences of
content 0x7E.
In AX8052F131 the meaning of address and control is
user defined. The Frame Check Sequence (FCS) can be
programmed to be CRC−CCITT, CRC−16 or CRC−32.
For details on implementing a HDLC communication see
the AX5031 Programming Manual.
Raw Mode
In Raw mode, the AX8052F131 does not perform any
packet delimiting or byte synchronization. It simply
serializes transmit bytes.
This mode is ideal for implementing legacy protocols in
software.
802.15.4 (ZigBee) DSSS
802.15.4 uses binary phase shift keying (PSK) with
300 kbit/s (868 MHz band) or 600 kbit/s (915 MHz band) on
the radio. The usable bit rate is only a 15^th of the radio bit
rate, however. A spreading function in the transmitter
expands the user bit rate by a factor of 15, to make the
transmission more robust.
In 802.15.4 mode, the AX8052F131 framing unit
performs the spreading function according to the 802.15.4
specification.
The 802.15.4 is a universal DSSS mode, which can be
used with any modulation or data rate as long as it does not
violate the maximum data rate of the modulation being used.
Therefore the maximum DSSS data rate is 16 kbps for FSK
and 40 kbps for ASK and PSK.
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