AMIS30512C5122G Datasheet, PDF (22/30 Pages) ON Semiconductor – Micro-Stepping Motor Driver

AMIS−30512
Byte 1 contains the Command and the SPI Register
Address and indicates to AMIS−30512 the chosen type of
operation and addressed register. Byte 2 contains data, or
sent from the Master in a WRITE operation, or received
from AMIS−30512 in a READ operation.
2 command types can be distinguished in the
communication between master and AMIS−30512:
• READ from SPI Register with address ADDR[4:0]:
CMD2 = “0”
• WRITE to SPI Register with address ADDR[4:0]:
CMD2 = “1”
READ Operation
If the Master wants to read data from Status or Control
Registers, it initiates the communication by sending a
READ command. This READ command contains the
address of the SPI register to be read out. At the falling edge
of the eight clock pulse the data−out shift register is updated
with the content of the corresponding internal SPI register.
In the next 8−bit clock pulse train this data is shifted out via
DO pin. At the same time the data shifted in from DI
(Master) should be interpreted as the following successive
command or is dummy data.
Registers are updated with the internal status at the rising
edge of the internal AMIS−30512 clock when CS = 1
CS
COMMAND
DI
READ DATA from ADDR1
DATA from previous command or
NOT VALID after POR or RESET
DATA
DO
OLD DATA or NOT VALID
COMMAND or DUMMY
DATA
DATA from ADDR1
Figure 18. Single READ operation where DATA from SPI register with
Address 1 is read by the Master
All 4 Status Registers (see SPI Status Registers) contain
7 data bits and a parity check bit. The most significant bit
(D7) represents a parity of D[6:0]. If the number of logical
ones in D[6:0] is odd, the parity bit D7 equals “1”. If the
number of logical ones in D[6:0] is even then the parity bit
D7 equals “0”. This simple mechanism protects against
noise and increases the consistency of the transmitted data.
If a parity check error occurs it is recommended to initiate
an additional READ command to obtain the status again.
Also the Control Registers (see SPI Control Registers) can
be read out following the same routine. Control Registers
don’t have a parity check.
The CSB line is active low and may remain low between
successive READ commands as illustrated in Figure 18.
There is however one exception. In case an error condition
is latched in one of Status Registers (see SPI Registers) the
ERRB pin is activated. (See Error Output). This signal flags
a problem to the external microcontroller. By reading the
Status Registers information about the root cause of the
problem can be determined. After this READ operation the
Status Registers are cleared. Because the Status Registers
and ERRB pin are only updated by the internal system clock
when the CSB line is high, the Master should force CSB high
immediately after the READ operation. For the same reason
it is recommended to keep the CSB line high always when
the SPI bus is idle.
WRITE Operation
If the Master wants to write data to a Control Register it
initiates the communication by sending a WRITE
command. This contains the address of the SPI register to
write to. The command is followed with a data byte. This
incoming data will be stored in the corresponding Control
Register after CSB goes from low to high! AMIS−30512
responds on every incoming byte by shifting out via DO the
data stored in the last received address.
It is important that the writing action (command − address
and data) to the Control Register is exactly 16 bits long. If
more or less bits are transmitted the complete transfer packet
is ignored.
A WRITE command executed for a read−only register
(e.g. Status Registers) will not affect the addressed register
and the device operation.
Because after a power−on−reset the initial address is
unknown the data shifted out via DO is not valid.
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