NCP1605 Datasheet, PDF (21/32 Pages) ON Semiconductor – Enhanced, High Voltage and Efficient Standby Mode, Power Factor Controller

NCP1605, NCP1605A
“pfcOK” signal of the block diagram, is high). This is
because, at the beginning of operation, the Pin 3 capacitor
must charge slowly and gradually for a soft−startup.
Remark: As shown in block diagram, the circuitry for
undershoots limitation is disabled as long as Pin 3 detects
standby conditions (V_Pin3 < 300 mV). This is to suppress the
risk of audible noise in standby thanks to the soft–start that
softens the bursts.
On−Time Control for Maximum Power Adjustment
As aforementioned, the NCP1605(A) processes the error
amplifier output voltage to form a signal (V_TON) that is used
by the PWM section to control the on−time. (V_TON)
compensates the relative weight of the dead−time sequences
measured during the precedent current cycles. During the
conduction time of the MOSFET, Pin 7 sources a current that
is proportional to the square of the voltage applied to Pin 4
(feedback pin). Practically, as Pin 4 receives a portion of the
output voltage (V_OUT), I_Pin7 is proportional to the square of
V_OUT.
The MOSFET turns off when the Pin 7 voltage exceeds
V_TON. Hence, the MOSFET on−time (t1) is given by:
t1
+
Cpin7 VTON
k VOUT²
where k is a constant.
The coil current averaged over one switching period is:
t
ICOIL
u
T
+
IIN(t)
+
VIN t1
2L
(t1
)
T
t2)
Where I_IN(t) and V_IN(t) are the instantaneous input current
and voltage, respectively, t₂ is the core reset time and T is the
switching period. Hence, the instantaneous input power is
given by the following equation:
PIN(t)
+
VIN(t)IIN(t)
+
Cpin7 VIN2
2 L k VOUT²
@
VTON
(t1
T
)
t2)
As aforementioned, we have: V_TON (t₁ + t₂)/T = V_REGUL
where V_REGUL is the signal outputted by the regulation
block. Hence, the average input power is:
t PIN
u+
Cpin7 Vac2
2 L k VOUT²
VREGUL
The maximum value of V_REGUL being 1 V, the maximum
power that can be delivered is:
t
PIN
u
MAX
+
Cpin7 Vac2
2 L k VOUT²
1V
To the light of the last equations, one can note that the PFC
power capability is inversely proportional to the square of the
output voltage. One sees that if the power demand is too high
to keep the regulation, (V_REGUL=1V) and the power delivery
depends on the output voltage level that stabilizes to the
following value:
Ǹ VOUT +
Cpin7 1 V
2 L k h POUT ^Vac
Where:
• P_OUT is the output power.
• And h is the efficiency.
Hence, one obtains the Follower Boost characteristics. The
“Follower Boost” is an operation mode where the
pre−converter output voltage stabilizes at a level that varies
linearly versus the ac line amplitude. This technique aims at
reducing the gap between the output and input voltages to
optimize the boost efficiency and minimize the cost of the
PFC stage (refer to the MC33260 data sheet for more
information, at:
http://www.onsemi.com/pub/Collateral/MC33260−D.PDF ).
Remark: the timing capacitor applied to Pin 7 is
discharged and maintained grounded when the drive is low.
Furthermore, the circuit compares the Pin 7 voltage to an
internal reference 50 mV and prevents the PWM latch from
being set as long as V_Pin7 is higher than this low threshold.
This is to guarantee that the timing capacitor is properly
discharged before starting a new cycle.
Current Sense and Zero Current Detection
The NCP1605(A) is designed to monitor a negative
voltage proportional to the coil current. Practically, a
current sense resistor (R_CS) is inserted in the return path to
generate a negative voltage proportional to the coil current
(V_CS). The circuit uses V_CS for two functions: the
limitation of the maximum coil current and the detection
of the core reset (coil demagnetization). To do so, the
circuit incorporates an operational amplifier that sources
the current necessary to maintain the CS pin voltage null
(refer to Figure 60). By inserting a resistor R_OCP between
the CS pin and R_CS, we adjust the CS pin current as follows:
* [RCS ICOIL] ) [ROCP Ipin5] + Vpin5 [ 0
Which leads to:
Ipin5
+
RCS
ROCP
ICOIL
In other words, the Pin 5 current is proportional to the coil
current.
I_Pin5 is utilized as follows:
• If I_Pin5 exceeds 250 mA, an overcurrent is detected and
the PWM latch is reset. Hence, the maximum coil
current is:
(ICOIL)max
+
ROCP
RCS
250
mA
The propagation delay (Ipin5 higher than 250 mA) to
(drive output low) is in the range of 100 ns, typically.
• The Pin 5 current is internally copied and sourced by
Pin 6. Place a resistor (R_Pin6) between Pin 6 and ground
to build a voltage proportional to the coil current. The
circuit detects the core reset when V_Pin6 drops below
100 mV, typically. The Pin 6 voltage equating:
Vpin6
+
Rpin6 @ Rcs
Rcs
@
ICOIL
,
the coil current threshold for zero current detection is:
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