NCP1562A Datasheet, PDF (21/26 Pages) ON Semiconductor – High Performance Active Clamp/Reset PWM Controller

NCP1562A, NCP1562B
The output overlap delay is adjusted by connecting a
resistor, R_D, from the t_D pin to ground. The overlap delay
is proportional to R_D. A minimum delay of 20 ns is
obtained by grounding the t_D pin.
The leading delay is purposely made longer than the
trailing delay. This allows the user to optimize the delay for
the turn on transition of the main switch and ensures the
active clamp switch always exhibits zero volt switching.
Analog and Power Ground (PGND)
The NCP1562 has an analog ground, GND, and a power
ground, PGND, terminal. GND is used for analog
connections such as V_REF, R_TC_T, feedforward among
others. PGND is used for high current connections such as
the internal output drivers. It is recommended to have
independent analog and power ground planes and connect
them at a single point, preferably at the ground terminal of
the system. This will prevent high current flowing on
PGND from injecting noise in GND. The PGND
connection should be as short and wide as possible to
reduce inductance- induced spikes.
Oscillator
The oscillator frequency and maximum duty cycle are
set by an R_TC_T divider from V_REF as shown in Figure 48.
A 500 mA current source (I_RTCT) discharges the timing
capacitor (C_T) upon reaching its peak threshold
(V_RTCT(peak)), typically 3.0 V. Once C_T reaches its valley
voltage (V_RTCT(valley)), typically 2.0 V, I_RTCT turns OFF
allowing C_T to charge back up through R_T. The resulting
waveform on the RTCT pin has a sawtooth like shape.
V_REF
Enable
R_T
3V
RTCT
I_RTCT
2V
C_T
Figure 48. Oscillator Configuration
OUT2 is set high once V_RTCT(valley) is reached, followed
by OUT1 delayed by the overlap delay. Once V_RTCT(peak)
is reached, OUT1 goes low, followed by OUT2 delayed by
t_D.
The duty cycle is the C_T charge time (t_RTCT(C)) minus the
overlap delay over the total charge and discharge (t_RTCT(D))
times. The charge and discharge times are calculated using
Equations 5 and 6. However, these equations are an
approximation as they do not take into account the
propagation delays of the internal comparator.
  tRTCT(C) = RTCT × ln
VRTCT(valley)-- VREF
VRTCT(peak)-- VREF
(eq. 5)
  tRTCT(D) = RTCT × ln
(IRTCT × RT) + VRTCT(peak)--VREF
(IRTCT × RT) + VRTCT(valley)--VREF
(eq. 6)
The duty cycle, D, is given by Equation 7.
Substituting Equations 5, 6, and 7, and after a little
D
=
tRTCT(C)-- tD
tRTCT(C) + tRTCT(D)
(eq. 7)
algebraic manipulation and replacing values, it simplifies
to:
  _{D =}
  ln
ln
VRTCT(valley)--VREF
VRTCT(peak)--VREF
--
tD
RTCT
VRTCT(valley)--VREF
VRTCT(peak)--VREF
×
(IRTCT×RT)+VRTCT(peak)--VREF
(IRTCT×RT)+VRTCT(valley)--VREF
(eq. 8)
It can be observed that D is set by R_T, C_T and t_D. This
equation has two variables and can be solved iteratively. In
to achieve a given duty cycle. Once the R_T is selected, C_T
is chosen to obtain the desired operating frequency using
general, the time delay is a small portion of the ON time and Equation 9.
can be ignored as a first approximation. R_T is then selected
  f =
RTCT × ln
1
VRTCT(valley)--VREF
VRTCT(peak)--VREF
×
(IRTCT×RT)+VRTCT(peak)--VREF
(IRTCT×RT)+VRTCT(valley)--VREF
(eq. 9)
Figures 23 through 26 show the frequency and duty cycle
variation vs R_T for several C_T values. R_T should not be less
than 6.0 kΩ. Otherwise, the R_TC_T charge current will
exceed the pulldown current and the oscillator will be in an
undefined state.
Synchronization
A proprietary bidirectional frequency synchronization
architecture allows multiple NCP1562 to synchronize in a
master- slave configuration. It can synchronize to
frequencies above or below the free running frequency.
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