NCP1611 Datasheet, PDF (20/28 Pages) ON Semiconductor – Enhanced, High-Efficiency Power Factor Controller

NCP1611
V_SE^B_N^O_S^p_Eⁱⁿpin
V to I
I_BO
I_REGUL
I_BO
converter
V_CV_Oc_No_Tn_Rtr_Ool_Lppinin
Multiplier
LLine
FFFcFoconnttrroollppinin
V to I
converter
I_REGUL
. I_REGUL= K V_REGUL
. . K_m I_REGUL I_BO
S^SU^UMM
+
R_RA_AM_MP_P
R_FF
0.75 V / 0.65¹V
pf^pc^fO^cOK^K
S^skK^ipIP²
Figure 61. Generation of the Current Information
Skip Mode
As illustrated in Figure 61, the circuit also skips cycles
near the line zero crossing where the current is very low. A
comparator monitors the pin 3 voltage (“FFcontrol”
voltage) and inhibits the drive when V_pin3 is lower than a
0.65 V internal reference. Switching resumes when V_pin3
exceeds 0.75 V (0.1 V hysteresis). This inhibits circuit
operation when the power transfer is particularly inefficient
at the expense of slightly increased current distortion. When
superior power factor is needed, this function can be
inhibited offsetting the “FFcontrol” pin by 0.75 V. The skip
mode capability is disabled whenever the PFC stage is not
in nominal operation (as dictated by the “pfcOK” signal −
see block diagram and “pfcOK Internal Signal” Section).
The circuit does not abruptly interrupt the switching when
V_pin3 goes below 0.65 V. Instead, the signal V_TON that
controls the on−time is gradually decreased by grounding
the V_REGUL signal applied to the V_TON processing block (see
Figure 9). Doing so, the on−time smoothly decays to zero in
three to four switching periods typically. Figure 62 shows
the practical implementation.
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