NCN49599_15 Datasheet, PDF (20/35 Pages) ON Semiconductor – Power Line Communication Modem

NCN49599
• CHIP_CLK is the output of the PLL and the input of
the timing generator. It runs 8 times faster than the bit
rate on the physical interface.
• BIT_CLK is only active at chip clock counter values
that are multiples of 8 (0, 8, .., 2872). It indicates the
start of the transmission of a new bit.
• BYTE_CLK is only active at chip clock counter values
that are multiples of 64 (0, 64, .., 2816). It indicates the
start of the transmission of a new byte.
• FRAME_CLK is only active at counter value 0; it
indicates the transmission or reception of a new frame.
• PRE_BYTE_CLK follows the same pattern as
BYTE_CLK, but precedes it by 8 chip clocks. It can be
used as an interrupt for the internal microcontroller and
Start of the physical subframe
indicates that a new byte for transmission must be
generated.
• PRE_FRAME_CLK follows the same pattern at
FRAME_CLK, but precedes it by 8 chip clocks. It can
be used as an interrupt for the internal microcontroller
and indicates that a new frame will start at the next
FRAME_CLK.
• PRE_SLOT is active between the rising edge of
PRE_FRAME_CLK and the rising edge of
FRAME_CLK. This signal can be provided at the
digital output pin DATA/PRES when R_CONF[7] = 0.
Thus, the external host controller may synchronize its
software with the internal FRAME_CLK of the
NCN49599. Refer to the SCI section and Table 26 for
details.
R_CHIP_CNT ^{2871 2872 2879 0 1 2 3 4 5 6 7 8 9}
CHIP_CLK
63 64 65
BIT_CLK
BYTE_CLK
FRAME _CLK
PRE_BYTE_CLK
PRE_FRAME _CLK
PRE_SLOT
Figure 20. Timing Signals
Transmitter Path Description (S−FSK Modulator)
The NCN49599 transmitter block (Figure 21) generates
the signal to be sent on the transmission channel. Most
commonly, the output is connected to a power amplifier
which injects the output signal on the mains through a
line−coupler.
As the NCN49599 is a half−duplex modem, this block is
not active when the modem is receiving.
The transmitter block is controlled by the microcontroller
core, which provided the bit sequence to be transmitted.
Direct digital synthesis (DDS) is employed to synthesize the
modulated signal (the Sine Wave Generator section); after a
conditioning step, this signal is converted to an analogue
voltage (the DA Converter section). Finally, an amplifier
with variable gain buffers the signal (the Amplifier with
ALC section) and outputs it on pin TX_OUT.
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