NCL30185 Datasheet, PDF (20/28 Pages) ON Semiconductor – Power Factor Corrected Quasi-Resonant Primary Side Current-Mode Controller

NCL30185
ZCD STOP ^VVS ^VREFX
V_CS
Power Factor and
PWM Latch reset
Constant−Current
Control
COMP
C1
Figure 59. Power Factor and Constant−Current Control
As illustrated in Figure 59, the V_S pin provides the
sinusoidal reference necessary for shaping the input current.
The obtained current reference is further modulated so that
when averaged over a half−line period, it is equal to the
output current reference (V_REFX). This averaging process is
made by an internal Operational Trans−conductance
Amplifier (OTA) and the capacitor connected to the COMP
pin (C1 of Figure 59). Typical COMP capacitance is 1 mF
and should not be less than 470 nF to ensure stability. The
COMP ripple does not affect the power factor performance
as the circuit digitally eliminates it when generating the
current setpoint.
If the V_S pin properly conveys the sinusoidal shape, power
factor will be close to unity and the Total Harmonic
Distortion (THD) will be low. In any case, the output current
will be well regulated following the equation below:
I_out
+
V_REFX
2N_PSR_sense
(eq. 1)
Where:
• N_PS is the secondary to primary transformer turns
N_PS = N_S/N_P
• R_sense is the current sense resistor (see Figure 1).
• V_REFX is the output current internal reference.
V_REFX = V_REF (250 mV typically) at full load.
The output current reference (V_REFX) is 250 mV typically
(V_REF). In the event that step dimming is engaged, V_REFX
takes a lower value based on the step−dimming level (see
“step dimming” section) or if the temperature is high enough
to activate the thermal fold−back (see “protections”
section).
If a major fault is detected, the circuit enters the
latched−off or auto−recovery mode and the COMP pin is
grounded (except in an UVLO condition). This ensures a
clean start−up when the circuit resumes operation.
Start−up Sequence
Generally an LED lamp is expected to emit light in < 1 sec
and typically within 300 ms. The start−up phase consists of
the time to charge the V_CC capacitor, initiate startup and
begin switching and the time to charge the output capacitor
until sufficient current flows into the LED string.
To speed−up this phase, the following defines the start−up
sequence:
• The COMP pin is grounded when the circuit is off. The
average COMP voltage needs to exceed the V_S pin
peak value to have the LED current properly regulated
(whatever the current target is). To speed−up the COMP
capacitance charge and shorten the start−up phase, an
internal 80−mA current source adds to the OTA sourced
current (60 mA max typically) to charge up the COMP
capacitance. The 80−mA current source remains on until
the OTA starts to sink current as a result of the COMP
pin voltage sufficient rise. At that moment, the COMP
pin being near its steady−state value, it is only driven
by the OTA.
• Whatever the step−dimming state is, the output current
reference is set maximum (V_REFX = V_REF) until the
ZCD pin voltage reaches the 1−V V_ZCD(short) threshold.
This prevents the circuit from detecting an output short
(AUX_SCP protection trips if the ZCD pin voltage
does not exceed 1−V V_ZCD(short) threshold within a
90−ms delay) just because dimming would make the
output voltage charge up slowly. If the system cannot
start−up in one V_CC cycle, the AUX_SCP 90−ms
blanking time is not reset and V_REFX remains
maximum for all the necessary V_CC cycles until the
ZCD pin voltage reaches the 1−V V_ZCD(short) threshold.
• If V_CC drops below the V_CC(off) threshold because the
circuit fails to start−up properly on the first attempt, a
new try takes place as soon as V_CC is recharged to
V_CC(on). The COMP voltage is not reset at that
moment. Instead, the new attempt starts with the
COMP level obtained at the end of the previous
operating phase.
• If the load is shorted, the circuit will operate in hiccup
mode with V_CC oscillating between V_CC(off) and
V_CC(on) until the AUX_SCP protection trips
(AUX_SCP is triggered if the ZCD pin voltage does
not exceed 1 V within a 90−ms operation period of time
thus indicating a short to ground of the ZCD pin or an
excessive load preventing the output voltage from
rising). The NCL30185A latches off in this case. With
the B version, the AUX_SCP protection forces the 4−s
auto−recovery delay to reduce the operation duty−ratio.
Figure 60 illustrates a start−up sequence with the output
shorted to ground, in this second case.
www.onsemi.com
20