NCL30085 Datasheet, PDF(20/27 Page) ON Semiconductor – Quasi-Resonant Primary Side Current-Mode Controller

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NCL30085 Datasheet, PDF (20/27 Pages) ON Semiconductor – Quasi-Resonant Primary Side Current-Mode Controller

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NCL30085

VCC

VCC(on)

VCC(off)

(â§â§â§ )

AUX_SCPtrips

time

DRV

as t1 + t2 + t3 = tOVLD

(tOVLD ^90 ms)

( ) trecovery ^4 s

time

Figure 59. Startâup Sequence in a Load Shortâcircuit Situation (autoârecovery version)

Step Dimming

The step dimming function decreases the output current

from 100% to 5% of its nominal value in 3 discrete steps.

The table below shows the different steps value and the

corresponding reference voltage value. Each time a

brownâout is detected, the output current is decreased by

decreasing the reference voltage VREF.

A counter is incremented by the BO_NOK (brownâout

not OK) signal and selects one of the four corresponding

reference thresholds: VREF, VREF70, VREF25, VREF5. After

counting up to 4, the counter is reset.

Table 4. DIMMING STEPS

Dimming Step

Iout

100%

70%

25%

Note:

The step dimming state is memorized until VCC crosses

VCC(reset) or VVS is below VBO(off) for 3 s (typical).

The circuit consumption is optimized (in particular, it

equals ICC(fault) when VCC is lower than VCC(off)) so that the

VCC voltage does not drop too fast for the step dimming

brownâout event.

The power supply designer should use a split VCC circuit

as shown in Figure 60 where a small capacitor C1 is used for

a fast startâup while a larger C2 capacitance provides the

necessary storage capability for step dimming. During step

dimming, at startup, the controller generates the first DRV

pulses after 1 timeâout pulse even if a higher valley number

is selected by VREFX. This avoids long startup time while

dimming at low output current value.

VCC

Figure 60. Split VCC Supply

The stepâdimming function is reset if the VS pin is

maintained below the VBO(off) brownâout threshold for the

Tstep_reset time. Tstep_reset is 3 s typically. In other words, any

brownâout event that is longer than Tstep_reset, leads the

controller to reâstart at 100% current setting.

Zero Crossing Detection Block

The ZCD pin detects when the drainâsource voltage of the

power MOSFET reaches a valley by crossing below the

55âmV internal threshold. At startup or in case of extremely

damped free oscillations, the ZCD comparator may not be

able to detect the valleys. To avoid such a situation, the

NCL30085 features a timeâout circuit that generates pulses

if the voltage on ZCD pin stays below the 55âmV threshold

for 6.5 ms. The timeâout also acts as a substitute clock for the

valley detection and simulates a missing valley in case the

free oscillations are too damped.

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