KLI-8023-D Datasheet, PDF (20/25 Pages) ON Semiconductor – Linear CCD Image Sensor

KLI−8023
AC Operating Conditions
Table 9. AC ELECTRICAL CHARACTERISTICS − AC TIMING REQUIREMENTS
Description
Symbol
Minimum Nominal Maximum
CCD Element Duration
1e (= 1/f_CLK)
167
1,000
−
H1A/B, H2A/B Rise Time
t_RISE
20
100
−
Line Integration Period
1L (= t_INT)
1.343
8,054
−
PD−CCD Transfer Period
t_PD
2666
16,000
−
Transfer Gate 1 Clear
t_TG1
167
1,000
−
Transfer Gate 2 Clear
t_TG2
167
1,000
−
Charge Drain Duration
t_DR
1,000
−
−
Reset Pulse Duration
t_RST
20
−
−
Clamp to H2 Delay
t_CD
6
−
−
Sample to Reset Edge Delay
t_SD
6
−
−
1. Minimum values given are for 6 MHz CCD operation.
2. Recommended delays for Correlated Double Sampling (CDS) for output.
3. Minimum value required to ensure proper operation, allowing for on-chip propagation delay.
Units
ns
ns
ms
ns
ns
ns
ns
ns
ns
ns
Notes
1e Count
8,054e Counts
16e Counts
1e Count
1e Count
3
1
2
2
Table 10. AC ELECTRICAL CHARACTERISTICS − CLOCK LEVEL CONDITIONS FOR OPERATION
Description
Symbol
Minimum Nominal Maximum
Units
Notes
CCD Readout Clocks High (n = A or B)
V_H1nH, V_H2nH
6.25
6.5
7.0
V
CCD Readout Clocks Low (n = A or B)
V_H1nL, V_H2nL
−0.1
0.0
0.1
V
1
Transfer Clocks High (n = 1 or 2)
V_TGnH
6.25
6.5
7.0
V
Transfer Clocks Low (n = 1 or 2)
V_TGnL
−0.1
0.0
0.1
V
1
Reset Clock High (Normal Mode)
V_fRH
6.25
6.5
7.0
V
Reset Clock High (High DR Mode)
V_fRH
11.5
12.0
12.5
V
Reset Clock Low
V_fRL
−0.1
0.0
0.1
V
1
Exposure Clocks High (n = R, G, B)
V_LOGnH
6.25
6.5
7.0
V
2
Exposure Clocks Low (n = R, G, B)
V_LOGnL
−0.1
0.0
0.1
V
1, 2
1. Care should be taken to insure that low rail overshoot does not exceed –0.5 VDC. Exceeding this value may result in non-photogenerated
charge being injected into the video signal.
2. Connect pin to ground potential for applications where exposure control is not required.
Table 11. CLOCK LINE CAPACITANCE
Description
Symbol
Minimum
Nominal
Maximum
Units
Notes
CHROMA
Phase 1 Clock Capacitance
C_f1
−
4,180
−
pF
1
Phase 2 Clock Capacitance
C_f2
−
2,000
−
pF
1
Transfer Gate 1 Capacitance
C_TG1
−
925
−
pF
Transfer Gate 2 Capacitance
C_TG2
−
475
−
pF
Exposure Gate Capacitance
C_LOG
−
190
−
pF
Reset Gate Capacitance
C_fR
−
11
−
pF
1. This is the total load capacitance per CCD phase. Since the CCDs are driven from both ends of the sensor, the effective load capacitance
per drive pin is approximately half the value listed.
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