AX8052F143 Datasheet, PDF (20/45 Pages) ON Semiconductor – SoC Ultra-Low Power RF-Microcontroller

AX8052F143
The AX8052 uses P or Code Space to access its program.
Code space may also be read using the MOVC instruction.
Smaller amounts of data can be placed in the Internal (see
Note) or Data Space. A distinction is made in the upper half
of the Data Space between direct accesses (MOV reg,addr;
MOV addr,reg) and indirect accesses (MOV reg,@Ri;
MOV @Ri,reg; PUSH; POP); Direct accesses are routed to
the Special Function Registers, while indirect accesses are
routed to the internal RAM.
NOTE: The origin of Internal versus External (X) Space
is historical. External Space used to be outside
of the chip on the original 8052
Microcontrollers.
Large amounts of data can be placed in the External or X
Space. It can be accessed using the MOVX instructions.
Special Function Registers, as well as additional
Microcontroller Registers (XREG) and the Radio Registers
(RREG) are also mapped into the X Space.
Detailed documentation of the Special Function Registers
(SFR) and additional Microcontroller Registers can be
found in the AX8052 Programming Manual.
The Radio Registers are documented in the AX5043
Programming Manual. Register Addresses given in the
AX5043 Programming Manual are relative to the beginning
of RREG, i.e. 0x4000 must be added to these addresses. It
is recommended that the AXSEM provided ax8052f143.h
header file is used; Radio Registers are prefixed with
AX5043_ in the ax8052f143.h header file to avoid clashes of
same−name Radio Registers with AX8052 registers.
Normally, accessing Radio Registers through the RREG
address range is adequate. Since Radio Register accesses
have a higher latency than other AX8052 registers, the
AX8052 provides a method for non−blocking access to the
Radio Registers. Accessing the RREG (nb) address range
initiates a Radio Register access, but does not wait for its
completion. The details of mechanism is documented in the
Radio Interface section of the AX8052 Programming
Manual.
The FLASH memory is organized as 64 pages of 1 kBytes
each. Each page can be individually erased. The write word
size is 16 Bits. The last 1 kByte page is dedicated to factory
calibration data and should not be overwritten.
Power Management
The microcontroller power mode can be selected
independently from the transceiver. The microcontroller
supports the following power modes:
Table 21. POWER MANAGEMENT
PCON
register
Name
Description
00
RUNNING
The microcontroller and all peripherals are running. Current consumption depends on the system clock
frequency and the enabled peripherals and their clock frequency.
01
STANDBY
The microcontroller is stopped. All register and memory contents are retained. All peripherals continue to
function normally. Current consumption is determined by the enabled peripherals. STANDBY is exited
when any of the enabled interrupts become active.
10
SLEEP
The microcontroller and its peripherals, except GPIO and the system controller, are shut down. Their
register settings are lost. The internal RAM is retained. The external RAM is split into two 4 kByte blocks.
Software can determine individually for both blocks whether contents of that block are to be retained or
lost. SLEEP can be exited by any of the enabled GPIO or system controller interrupts. For most
applications this will be a GPIO or wakeup timer interrupt.
11
DEEPSLEEP The microcontroller, all peripherals and the transceiver are shut down. Only 4 bytes of scratch RAM are
retained. DEEPSLEEP can only be exited by tying the PB3 pin low.
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