NLSF302_06 Datasheet, PDF (2/4 Pages) ON Semiconductor – Quad 2−Input NOR Gate

NLSF302
16
15
14
13
16
A1
1
B1
4
A2
5
B2
7
A3
8
B3
10
A4
12
B4
15
Y1
3
Y2
Y=A+B
9
Y3
13
Y4
Figure 1. LOGIC DIAGRAM
B1 ₁
NC ₂
Y2 ₃
A2 ₄
NLSF302
MN Package
(Top View)
12 B4
11 NC
10 A4
9 Y3
5
6
7
8
Figure 2. PIN ASSIGNMENT (QFN−16)
MAXIMUM RATINGS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _Parameter
Symbol
Value
Unit
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC Supply Voltage}
V_CC
– 0.5 to + 7.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{DC Input Voltage}
V_in
– 0.5 to + 7.0
V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{DC Output Voltage}
V_out – 0.5 to V_CC + 0.5 V
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Input Diode Current}
I_IK
− 20
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Output Diode Current}
I_OK
± 20
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{DC Output Current, per Pin}
I_out
± 25
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{DC Supply Current, VCC and GND Pins}
I_CC
± 50
mA
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Power Dissipation in Still Air}
P_D
450
mW
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Storage Temperature}
T_stg
– 65 to + 150
°C
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress}
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol Min
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC Supply Voltage}
V_CC
2.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC Input Voltage}
V_in
0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{DC Output Voltage}
V_out
0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Operating Temperature}
T_A
−40
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Input Rise and Fall Time}
V_CC = 3.3 V ± 0.3 V t_r, t_f
0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ^{VCC =5.0 V ± 0.5 V}
0
Max Unit
5.5
V
5.5
V
V_CC
V
+85
°C
100 ns/V
20
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V_in and
V_out should be constrained to the
range GND v (V_in or V_out) v V_CC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V_CC).
Unused outputs must be left open.
http://onsemi.com
2