NCP4688DSN28T1G Datasheet, PDF (2/14 Pages) ON Semiconductor – 150 mA, Low Noise, LDO Linear Voltage Regulator

NCP4688xxxx
NCP4688
NCP4688D
Vin
Vout _Vin
Vout
Vref
CE
Noise Reduction
Vref
CE
Current Limit
GND
Noise Reduction
Current Limit
Figure 2. Simplified Schematic Block Diagram
GND
Table 1. PIN FUNCTION DESCRIPTION
Pin No.
SOT−23−5
Pin No.
DFN 1x1
Pin Name
1
4
VIN
2
2
GND
3
3
CE
4
NC
5
1
VOUT
*EP
EP
Description
Input pin
Ground pin
Chip enable pin (“H” active)
Non connected
Output pin
Exposed Pad (leave floating or connect to GND)
Table 2. ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Value
Unit
Input Voltage
Output Voltage
Chip Enable Input
Power Dissipation SOT−23−5
Power Dissipation mDFN 1.0 x 1.0 mm
V_IN
0−6V
V
V_OUT
−0.3 to V_IN + 0.3
V
V_CE
0−6V
V
P_D
420
mW
400
Junction Temperature
T_J
−40 to 150
°C
Storage Temperature
T_STG
−55 to 125
°C
ESD Capability, Human Body Model (Note 1)
ESD_HBM
2000
V
ESD Capability, Machine Model (Note 1)
ESD_MM
200
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. This device series incorporates ESD protection and is tested by the following methods:
ESD Human Body Model tested per AEC−Q100−002 (EIA/JESD22−A114)
ESD Machine Model tested per AEC−Q100−003 (EIA/JESD22−A115)
Latchup Current Maximum Rating tested per JEDEC standard: JESD78
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