NBSG53A_06 Datasheet, PDF (2/18 Pages) ON Semiconductor – 2.5V/3.3V SiGe Selectable Differential Clock and Data D Flip−Flop/Clock Divider with Reset and OLS

NBSG53A
1
2
A VTD
D
3
4
D
VTD
V_CC R SEL OLS
16 15 14 13
Exposed Pad
(EP)
B
CLK VTCLK V_CC
Q
C
CLK VTCLK V_EE
Q
VTCLK 1
CLK 2
CLK 3
NBSG53A
12 V_EE
11 Q
10 Q
D
V_CC
R
SEL OLS
VTCLK ₄
5 678
9 ^VCC
Figure 1. BGA−16 Pinout (Top View)
VTD D D VTD
Figure 2. QFN−16 Pinout (Top View)
Table 1. Pin Description
Pin
BGA
C2
C1
QFN
1
2
Name
VTCLK
CLK
I/O
−
ECL, CML,
LVCMOS,
LVDS, LVTTL
Input
Description
Internal 50 W Termination Pin. See Table 4.
Inverted Differential Input.
B1
3
CLK
ECL, CML, Noninverted Differential Input.
LVCMOS,
LVDS, LVTTL
Input
B2
4
VTCLK
−
Internal 50 W Termination Pin. See Table 4.
A1
5
VTD
−
Internal 50 W termination pin. See Table 4.
A2
6
D
ECL, CML, Inverted Differential Input.
LVCMOS,
LVDS, LVTTL
Input
A3
7
D
ECL, CML, Noninverted Differential Input.
LVCMOS,
LVDS, LVTTL
Input
A4
D1,B3
B4
C4
C3
D4
8
9,16
10
11
12
13
VTD
V_CC
Q
Q
V_EE
OLS*
−
−
RSECL Output
RSECL Output
−
Input
Internal 50 W Termination Pin. See Table 4.
Positive Supply Voltage
NonInverted Differential Output. Typically Terminated with 50 W Resistor to
V_TT = V_CC − 2 V.
Inverted Differential Output. Typically Terminated with 50 W Resistor to
V_TT = V_CC − 2 V.
Negative Supply Voltage
Input Pin for the Output Level Select (OLS). See Table 2.
D3
14
SEL
LVECL,
Select Logic Input. Internal 75 kW to V_EE.
LVCMOS,
LVTTL Input
D2
15
R
LVECL,
Reset D Flip−Flop. Internal 75 kW to V_EE.
LVCMOS,
LVTTL Input
N/A
−
EP
Exposed Pad. (Note 1)
1. All V_CC and V_EE pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat−sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination volt-
age, and if no signal is applied then the device will be susceptible to self−oscillation.
3. When an output level of 400 mV is desired and V_CC − V_EE > 3.0 V, 2KW resistor should be connected from OLS pin to V_EE.
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