NBC12439_09 Datasheet, PDF (2/21 Pages) ON Semiconductor – 3.3V/5V Programmable PLL Synthesized Clock Generator

NBC12439, NBC12439A
XTAL_SEL
15
FREF_EXT
3
4
10−20MHz
5
6
OE
28
S_LOAD
7
P_LOAD
27
S_DATA
26
S_CLOCK
PWR_DOWN +3.3 or 5.0 V
2
F_REF
PHASE
B2
DETECTOR
VCO
POWER
DOWN
XTAL1
OSC
XTAL2
7−BIT B M
COUNTER
B2
400−800
MHz
LATCH
BN
(1, 2, 4, 8)
LATCH
1
PLL_V_CC
+3.3 or 5.0 V
21, 25
V_CC
24
23
FOUT
FOUT
20
TEST
0
1
7−BIT SR
0
1
2−BIT SR
LATCH
3−BIT SR
8 → 14
17, 18
7
M[6:0]
2
N[1:0]
Figure 1. Block Diagram (28−Lead PLCC)
22, 19
Table 1. Output Division
N [1:0]
00
01
10
11
Output Division
2
4
8
1
Table 2. XTAL_SEL And OE
Input
0
1
PWR_DOWN
XTAL_SEL
OE*
F_OUT
FREF_EXT
Outputs Disabled
F_OUT B 16
XTAL
Outputs Enabled
*When disabled, FOUT goes LOW, FOUT goes HIGH.
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