N01S830HA_16 Datasheet, PDF (2/13 Pages) ON Semiconductor – 1 Mb Ultra-Low Power Serial SRAM

N01S830HA, N01S830BA
Table 1. DEVICE OPTIONS
Device / Part Number
N01S830HAT22
N01S830BAT22
Power Supply
HV 2.5 V − 5.5 V
HV 2.5 V − 5.5 V
Table 2. PIN NAMES
CS
SCK
Pin Name
SI / SIO0
SO / SIO1
NC / SIO2
HOLD / SIO3
VBAT
V_CC
V_SS
Speed
20 MHz for I−Temp,
16 MHz E−Temp
20 MHz for I−Temp,
16 MHz E−Temp
Package
TSSOP−8
Temperature
Range
I, E
Function
HOLD
TSSOP−8
I, E
BBU − Battery Back-up
Pin Function
Chip Select
Serial Clock
Data Input − SPI mode
Data Input/Output 0 − DUAL and QUAD mode
Data Output − SPI mode
Data Input/Output 1 − DUAL and QUAD mode
No Connect − SPI and DUAL mode
Data Input/Output 2 − QUAD mode
HOLD Version
HOLD Input − SPI and DUAL mode
Data Input/Output 3 − QUAD mode
BBU Version
Battery Supply − SPI and DUAL mode
Power
Ground
SCK
CS
SI / SIO0
SO / SIO1
SIO2
HOLD / SIO3
(HOLD Version)
Interface
Circuitry
Decode
Logic
Control
Logic
Data Flow
Circuitry
SRAM
Array
VBAT
(BBU Version)
Battery Controls
Figure 1. Functional Block Diagram
Table 3. CONTROL SIGNAL DESCRIPTIONS
Signal
Mode
Used
Name
Description
CS
All
Chip Select A low level selects the device and a high level puts the device in standby mode. If CS is brought
high during a program cycle, the cycle will complete and then the device will enter standby mode.
When CS is high, SO is in high-Z. CS must be driven low after power-up prior to any sequence
being started.
SCK
All
Serial Clock Synchronizes all activities between the memory and controller. All incoming addresses, data and
instructions are latched on the rising edge of SCK. Data out is updated after the falling edge of
SCK.
SI
SPI Serial Data In Receives instructions, addresses and data on the rising edge of SCK.
SO
SPI Serial Data Out Data is transferred out after the falling edge of SCK.
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