MC74LCX573_13 Datasheet, PDF (2/9 Pages) ON Semiconductor – Low-Voltage CMOS Octal Transparent Latch Flow Through Pinout

MC74LCX573
V_CC O0 O1 O2 O3 O4 O5 O6 O7 LE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
Figure 1. Pinout (Top View)
PIN NAMES
Pins
OE
LE
D0−D7
O0−O7
Function
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
1
OE
11
LE
2
D0
3
D1
4
D2
5
D3
6
D4
7
D5
8
D6
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
19
O0
18
O1
17
O2
16
O3
15
O4
14
O5
13
O6
9
D7
LE
Q
D
12
O7
Figure 2. Logic Diagram
TRUTH TABLE
Inputs
Outputs
OE
LE
Dn
On
Operating Mode
L
H
H
H
L
H
L
L
Transparent (Latch Disabled); Read Latch
L
L
h
H
L
L
l
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
Z
H
H
L
Z
Transparent (Latch Disabled); Disabled Outputs
H
L
h
Z
H
L
l
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level;
h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
NC = No Change, State Prior to the Latch Enable High−to−Low Transition
X = High or Low Voltage Level or Transitions are Acceptable
Z = High Impedance State
For I_CC Reasons DO NOT FLOAT Inputs
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