MC74LCX373_13 Datasheet, PDF (2/9 Pages) ON Semiconductor – Low-Voltage CMOS Octal Transparent Latch

MC74LCX373
V_CC O7 D7 D6 O6 O5 D5 D4 O4 LE
20 19 18 17 16 15 14 13 12 11
1 2 3 4 5 6 7 8 9 10
OE O0 D0 D1 O1 O2 D2 D3 O3 GND
Figure 1. Pinout (Top View)
PIN NAMES
PINS
OE
LE
D0−D7
O0−O7
FUNCTION
Output Enable Input
Latch Enable Input
Data Inputs
3−State Latch Outputs
1
OE
11
LE
3
D0
4
D1
7
D2
8
D3
13
D4
14
D5
17
D6
18
D7
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
LE
Q
D
2
O0
5
O1
6
O2
9
O3
12
O4
15
O5
16
O6
19
O7
Figure 2. Logic Diagram
TRUTH TABLE
INPUTS
OUTPUTS
OE
LE
Dn
On
L
H
H
H
L
H
L
L
OPERATING MODE
Transparent (Latch Disabled); Read Latch
L
L
h
H
L
L
l
L
Latched (Latch Enabled) Read Latch
L
L
X
NC
Hold; Read Latch
H
L
X
Z
Hold; Disabled Outputs
H
H
H
Z
H
H
L
Z
Transparent (Latch Disabled); Disabled Outputs
H
L
h
Z
H
L
l
Z
Latched (Latch Enabled); Disabled Outputs
H = High Voltage Level
h = High Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
L = Low Voltage Level
l = Low Voltage Level One Setup Time Prior to the Latch Enable High−to−Low Transition
NC = No Change, State Prior to the Latch Enable High−to−Low Transition
X = High or Low Voltage Level or Transitions are Acceptable
Z = High Impedance State
For I_CC Reasons DO NOT FLOAT Inputs
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