MC74HCT573ADWG Datasheet, PDF (2/8 Pages) ON Semiconductor – Octal 3-State Noninverting Transparent Latch with LSTTL Compatible Inputs

MC74HCT573A
LOGIC DIAGRAM
DATA
INPUTS
D0 ²
D1 ³
D2 ⁴
D3 ⁵
D4 ⁶
D5 ⁷
D6 ⁸
D7 ⁹
LATCH ENABLE ¹¹
OUTPUT ENABLE ¹
19 _Q0
18 _Q1
17 _Q2
16 _Q3
15 _Q4
14 _Q5
13 _Q6
12 _Q7
NONINVERTING
OUTPUTS
PIN 20 = V_CC
PIN 10 = GND
FUNCTION TABLE
Inputs
Output Latch
Enable Enable D
Output
Q
L
H
H
H
L
H
L
L
L
L
X No Change
H
X
X
Z
X = Don’t Care
Z = High Impedance
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Design Criteria}
Value
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Count*}
58.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Propagation Delay}
1.5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Internal Gate Power Dissipation}
5.0
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{Speed Power Product}
0.0075
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ _{*Equivalent to a two−input NAND gate.}
Units
ea
ns
μW
pJ
PIN ASSIGNMENT
OUTPUT
ENABLE
1
D0 2
20 V_CC
19 Q0
D1 3
18 Q1
D2 4
17 Q2
D3 5
16 Q3
D4 6
15 Q4
D5 7
14 Q5
D6 8
13 Q6
D7 9
GND 10
12 Q7
11 ^LATCH
ENABLE
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2