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MC74HC259A Datasheet, PDF (2/9 Pages) ON Semiconductor – 8-Bit Addressable Latch 1-of-8 Decoder
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MC74HC259A
ADDRESS
INPUTS
A0 1
A1 2
A2 3
DATA IN 13
RESET 15
ENABLE 14
4 Q0
5 Q1
6 Q2
7 Q3
9 Q4
10 Q5
11 Q6
12 Q7
NONINVERTING
OUTPUTS
PIN 16 = VCC
PIN 8 = GND
Figure 1. Logic Diagram
LATCH SELECTION TABLE
Address Inputs
A2
A1
A0
L
L
L
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
Latch Addressed
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
VCC DC Supply Voltage (Referenced to GND)
−0.5 to +7.0
V
Vin DC Input Voltage (Referenced to GND)
−0.5 to VCC + 0.5 V
Vout DC Output Voltage (Referenced to GND)
−0.5 to VCC + 0.5 V
Iin
DC Input Current, per Pin
±20
mA
Iout DC Output Current, per Pin
±25
mA
ICC DC Supply Current, VCC and GND Pins
±50
mA
PD Power Dissipation in Still Air,
SOIC Package
500
mW
TSSOP Package
450
Tstg Storage Temperature
−65 to + 150
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
VCC DC Supply Voltage (Referenced to GND)
2.0
Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0
TA
Operating Temperature, All Package Types
−55
tr, tf
Input Rise and Fall Time
(Figure 2)
VCC = 2.0 V 0
VCC = 3.0 V 0
VCC = 4.5 V 0
VCC = 6.0 V 0
Max Unit
6.0 V
VCC
V
+125 °C
1000 ns
600
500
400
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
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