MC74AC373 Datasheet, PDF (2/12 Pages) Motorola, Inc – OCTAL TRANSPARENT LATCH WITH 3-STATE OUTPUTS

MC74AC373, MC74ACT373
TRUTH TABLE
Inputs
Outputs
OE
LE
D_n
O_n
H
X
X
Z
L
H
L
L
L
H
H
H
L
L
X
O₀
H = HIGH Voltage Level
L = LOW Voltage Level
Z = High Impedance
X = Immaterial
O₀ = Previous O₀ before LOW-to-HIGH Transition of Clock
D₀
D₁
D₂
D₃
FUNCTIONAL DESCRIPTION
The MC74AC373/74ACT373 contains eight D−type
latches with 3−state standard outputs. When the Latch
Enable (LE) input is HIGH, data on the D_n inputs enters the
latches. In this condition the latches are transparent, i.e., a
latch output will change state each time its D input changes.
When LE is LOW, the latches store the information that was
present on the D inputs a setup time preceding the
HIGH−to−LOW transition of LE. The 3-state standard
outputs are controlled by the Output Enable (OE) input.
When OE is LOW, the standard outputs are in the 2−state
mode. When OE is HIGH, the standard outputs are in the
high impedance mode but this does not interfere with
entering new data into the latches.
D₄
D₅
D₆
D₇
D
D
D
D
D
D
D
D
O
O
O
O
O
O
O
O
G
G
G
G
G
G
G
G
LE
OE
NOTE: This diagram is provided only for the understanding of logic operations and
should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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