MC74AC259_15 Datasheet, PDF (2/9 Pages) ON Semiconductor – 8-Bit Addressable Latch

MC74AC259, MC74ACT259
MODE SELECT−FUNCTION TABLE
Operating
Inputs
Outputs
Mode
MR E D A₀ A₁ A₂ Q₀
Q₁
Q₂
Q₃
Q₄
Q₅
Q₆
Q₇
Master Reset L H X X X X L
L
L
L
L
L
L
L
L L d L L L Q=d L
L
L
L
L
L
L
L L d H L L L Q=d L
L
L
L
L
L
Demultiplex
L LdLHL L
L Q=d L
L
L
L
L
(Active HIGH
Decoder when
•
•
•
•
•
•
•
•
•
•
•
•
•
•
D = H)
• ••••• •
•
•
•
•
•
•
•
• ••••• •
•
•
•
•
•
•
•
L L dHHH L
L
L
L
L
L
L Q=d
Store
(Do Nothing)
H H X X X X q₀
q₁
q₂
q₃
q₄
q₅
q₆
q₇
H L d L L L Q = d q₁
q₂
q₃
q₄
q₅
q₆
q₇
H L d H L L q₀ Q = d q₂
q₃
q₄
q₅
q₆
q₇
Addressable
Latch
H L d L H L q₀
• ••••• •
q₁ Q = d q₃
•
•
•
q₄
•
q₅
•
q₆
•
q₇
•
• ••••• •
•
•
•
•
•
•
•
• ••••• •
•
•
•
•
•
•
•
H L d H H H q₀
q₁
q₂
q₃
q₄
q₅
q₆ Q = d
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
d = HIGH or LOW Data one setup time prior to the LOW−to−HIGH Enable transition
q = Lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed
or cleared.
FUNCTIONAL DESCRIPTION
The MC74AC259/74ACT259 has four modes of
operation as shown in the Mode Selection Table. In the
addressable latch mode, data on the Data line (D) is written
into the addressed latch. The addressed latch will follow the
data input with all non−addressed latches remaining in their
previous states in the memory mode. All latches remain in
their previous state and are unaffected by the Data or
Address inputs.
In the one−of−eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other outputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the MC74AC/ACT259 as an addressable
latch, changing more than one bit of the address could
impose a transient wrong address. Therefore, this should
only be done while in the memory mode. The Mode Select
Function Table summarizes the operations of the
MC74AC/ACT259.
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