MC74AC253_15 Datasheet, PDF (2/9 Pages) ON Semiconductor – Dual 4-Input Multiplexer with 3-State Outputs

MC74AC253, MC74ACT253
TRUTH TABLE
Select
Inputs
Data Inputs
Output
Enable
S₀ S₁
I₀
I₁
I₂
I₃
OE
X
X
X
X
X
X
H
L
L
L
X
X
X
L
L
L
H
X
X
X
L
H
L
X
L
X
X
L
H
L
X
H
X
X
L
L
H
X
X
L
X
L
L
H
X
X
H
X
L
H
H
X
X
X
L
L
H
H
X
X
X
H
L
Address inputs S₀ and S₁ are common to both sections.
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
Outputs
Z
Z
L
H
L
H
L
H
L
H
FUNCTIONAL DESCRIPTION
The MC74AC253/74ACT253 contains two identical
4−input multiplexers with 3−state outputs. They select two
bits from four sources selected by common Select inputs (S₀,
S₁). The 4−input multiplexers have individual Output
Enable (OE_a, OE_b) inputs which, when HIGH, force the
outputs to a high impedance (High Z) state. This device is the
logic implementation of a 2−pole, 4−position switch, where
the position of the switch is determined by the logic levels
OE_b
I_3b
I_2b
I_1b
I_0b
S₀
OE_a I_0a I_1a I_2a I_3a I_0b I_1b I_2b I_3b OE_b
S₀
S₁
Z_a
Z_b
Figure 2. Logic Symbol
supplied to the two select inputs. The logic equations for the
outputs are shown:
Z_a = OE_a•(I_0a•S₁•S₀+I_1a•S₁•S₀+
I_2a•S₁•S₀+I_3a•S₁•S₀)
Z_b = OE_b•(I_0b•S₁•S₀+I_1b•S₁•S₀+
I_2b•S₁•S₀+I_3b•S₁•S₀)
If the outputs of 3−state devices are tied together, all but
one device must be in the high impedance state to avoid high
currents that would exceed the maximum ratings. Designers
should ensure that Output Enable signals to 3−state devices
whose outputs are tied together are designed so that there is
no overlap.
S₁
I_3a
I_2a
I_1a
I_0a
OE_a
Z_b
Z_a
NOTE: This diagram is provided only for the understanding of logic operations
and should not be used to estimate propagation delays.
Figure 3. Logic Diagram
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