MC74AC174 Datasheet, PDF (2/9 Pages) ON Semiconductor – Hex D Flip−Flop with Master Reset

MC74AC174, MC74ACT174
D₀ D₁ D₂ D₃ D₄ D₅
CP
MR
Q₀ Q₁ Q₂ Q₃ Q₄ Q₅
Figure 2. Logic Symbol
FUNCTIONAL DESCRIPTION
The MC74AC174/74ACT174 consists of six
edge−triggered D flip−flops with individual D inputs and Q
outputs. The Clock (CP) and Master Reset (MR) are
common to all flip−flops. Each D input’s state is transferred
to the corresponding flip−flop’s output following the
LOW−to−HIGH Clock (CP) transition. A LOW input to the
Master Reset (MR) will force all outputs LOW independent
of Clock or Data inputs. The MC74AC174/ 74ACT174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.
MR CP D₅
D₄
D₃
D₂
D₁
D₀
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
DQ
CP
CD
Q₅
Q₄
Q₃
Q₂
Q₁
Q₀
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays. _{Figure 3. Logic Diagram}
MAXIMUM RATINGS*
Symbol
Parameter
Value
Unit
V_CC
V_IN
V_OUT
I_IN
I_OUT
I_CC
T_stg
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Sink/Source Current, per Pin
DC V_CC or GND Current per Output Pin
Storage Temperature
−0.5 to +7.0
V
−0.5 to V_CC +0.5
V
−0.5 to V_CC +0.5
V
±20
mA
±50
mA
±50
mA
−65 to +150
°C
*Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recom-
mended Operating Conditions.
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