MC74AC138DR2G Datasheet, PDF (2/11 Pages) ON Semiconductor – Decoder/Demultiplexer

MC74AC138, MC74ACT138
FUNCTIONAL DESCRIPTION
The MC74AC138/74ACT138 high−speed 1−of−8
decoder/demultiplexer accepts three binary weighted inputs
(A₀, A₁, A₂) and, when enabled, provides eight mutually
exclusive active−LOW outputs (O₀−O₇). The
MC74AC138/74ACT138 features three Enable inputs, two
active−LOW (E₁, E₂) and one active−HIGH (E₃). All
outputs will be HIGH unless E₁ and E₂ are LOW and E₃ is
HIGH. This multiple enabled function allows easy parallel
expansion of the device to a 1−of−32 (5 lines to 32 lines)
decoder with just four MC74AC138/74ACT138 devices
and one inverter (See Figure 4). The
MC74AC138/74ACT138 can be used as an 8−output
demultiplexer by using one of the active LOW Enable inputs
as the data input and the other Enable inputs as strobes. The
Enable inputs which are not used must be permanently tied
to their appropriate active−HIGH or active−LOW state.
TRUTH TABLE
Inputs
Outputs
E₁ E₂ E₃ A₀ A₁ A₂ O₀ O₁ O₂ O₃ O₄ O₅ O₆ O₇
H X X X X XHHHHHHHH
X H X X X XHHHHHHHH
X
X
L
X
X
X
H
H
H
H
H
H
H
H
L
L
H
L
L
L
L
H
H
H
H
H
H
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
L
L
H
L
H
L
H
H
L
H
H
H
H
H
L
L
H
H
H
L
H
H
H
L
H
H
H
H
L
L
H
L
L
H
H
H
H
H
L
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
H
L
L
H
H
H
H
H
H
H
H
H
H
H
L
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
A₂ A₁
A₀
E₁ E₂ E₃
0₇
0₆
0₅
0₄
0₃
0₂
0₁
0₀
NOTE:
This diagram is provided only for the understanding of logic
operations and should not be used to estimate propagation
delays.
Figure 3. Logic Diagram
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