MC10EP35_16 Datasheet, PDF (2/10 Pages) ON Semiconductor – ECL JK Flip‐Flop

MC10EP35, MC100EP35
J1
K2
CLK 3
RESET 4
J
K
Flip Flop
R
8 V_CC
7Q
6Q
5 V_EE
Figure 1. 8-Lead Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK*
J*, K*
ECL Clock Inputs
ECL Signal Inputs
RESET*
ECL Asynchronous Reset
Q, Q
ECL Data Outputs
V_CC
Positive Supply
V_EE
Negative Supply
EP
(DFN−8 only) Thermal exposed pad must
be connected to a sufficient thermal con-
duit. Electrically connect to the most nega-
tive supply (GND) or leave unconnected,
floating open.
* Pins will default LOW when left open.
Table 2. TRUTH TABLE
J
K
RESET
CLK
L-
L-
L
Z
L-
H
L
Z
H-
L
L
Z
H-
H
L
Z
X
X
H
X
Z = LOW to HIGH Transition
Qn+1
Qn
L
H
Qn
L
Table 3. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOIC−8 NB
TSSOP−8
DFN−8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
75 kW
N/A
> 4 kV
> 200 V
> 2 kV
Pb-Free Pkg
Level 1
Level 3
Level 1
UL−94 V−0 @ 0.125 in
77 Devices
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