MC100LVEL14_16 Datasheet, PDF (2/7 Pages) ON Semiconductor – 3.3 V ECL 1:5 Clock Distribution Chip

MC100LVEL14
V_CC EN V_CC NC SCLK CLK CLK V_BB SEL V_EE
20 19 18 17 16 15 14 13 12 11
10
D
Q
1 2 3 4 5 6 7 8 9 10
Q0 _Q0 Q1 _Q1 Q2 _Q2 Q3 _Q3 Q4 _Q4
Warning: All V_CC and V_EE pins must be externally connected
to Power Supply to guarantee proper operation.
Figure 1. Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN
FUNCTION
CLK, CLK
ECL Diff Clock Inputs
SCLK
ECL Scan Clock Input
EN
ECL Sync Enable
SEL
ECL Clock Select Input
Q_0−4, Q_0−4
V_BB
V_CC
V_EE
NC
ECL Diff Clock Outputs
Reference Voltage Output
Positive Supply
Negative Supply
No Connect
Table 2. FUNCTION TABLE
CLK
SCLK
SEL
EN
Q
L
X
L
H
X
L
X
L
H
X
H
H
X
X
X
L
L
L
H
L
L
L
H
H
L*
*On next negative transition of CLK or SCLK
X = Don’t Care
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V_CC PECL Mode Power Supply
V_EE
NECL Mode Power Supply
V_I
PECL Mode Input Voltage
NECL Mode Input Voltage
I_out
Output Current
V_EE = 0 V
V_CC = 0 V
V_EE = 0 V
V_CC = 0 V
Continuous
Surge
V_I ≤ V_CC
V_I ≥ V_EE
8 to 0
V
−8 to 0
V
6 to 0
V
−6 to 0
50
mA
100
I_BB
V_BB Sink/Source
T_A
Operating Temperature Range
T_stg
Storage Temperature Range
q_JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−20 WB
SOIC−20 WB
±0.5
−40 to +85
−65 to +150
90
60
mA
°C
°C
°C/W
q_JC
Thermal Resistance (Junction-to-Case)
T_sol
Wave Solder
Standard Board
< 2 to 3 sec @ 260°C
SOIC−20 WB
30 to 35
265
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
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