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| MC100EPT24_06 Datasheet, PDF (2/8 Pages) ON Semiconductor – 3.3V LVTTL/LVCMOS to Differential LVECL Translator | |||
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MC100EPT24
VEE 1
LVTTL
D2
NC 3
8 VCC
7Q
LVECL
6Q
NC 4
5 GND
Figure 1. 8âLead Pinout (Top View) and Logic Diagram
Table 1. PIN DESCRIPTION
PIN
Q, Q
D
VCC
GND
VEE
NC
FUNCTION
Differential LVECL Outputs
LVTTL Input
Positive Supply
Ground
Negative Supply
No Connect
EP
Exposed pad must be connected
to a sufficient thermal conduit.
Electrically connect to the most
negative supply or leave floating
open.
Table 2. ATTRIBUTES
Characteristics
Internal Input Pulldown Resistor
Internal Input Pullup Resistor
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1)
SOICâ8
TSSOPâ8
DFN8
Flammability Rating
Oxygen Index: 28 to 34
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Value
N/A
N/A
> 4 kV
> 200 V
> 2 kV
Pb Pkg
PbâFree Pkg
Level 1
Level 1
Level 1
Level 1
Level 3
Level 1
UL 94 Vâ0 @ 0.125 in
181 Devices
http://onsemi.com
2
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