LMV821 Datasheet, PDF (2/16 Pages) National Semiconductor (TI) – Low Voltage, Low Power, R-to-R Output, 5 MHz Op Amps

LMV821, LMV822, LMV824
MARKING DIAGRAMS
SC−70
Micro8
8
AAEMG
G
AAE
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
V822
AYWG
G
1
V822
A
Y
W
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−8
8
V822
ALYWG
G
1
V822
A
L
Y
W
G
= Specific Device Code
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
SOIC−14
14
LMV824G
AWLYWW
1
LMV824 = Specific Device Code
A
= Assembly Location
WL = Wafer Lot
Y
= Year
WW = Work Week
G
= Pb−Free Package
TSSOP−14
14
LMV
824
ALYWG
G
1
LMV824 = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
SC70−5
Micro8/SOIC−8
SOIC−14
TSSOP−14
1
+IN
5
V⁺
OUT A ₁
2
V^−
+
−
3
−IN
IN A− 2
4
IN A+ ₃
OUTPUT
(Top View)
V− ₄
A
−+
B
+−
(Top View)
8 ^V+
OUT A 1
IN A− 2
7 OUT B ^{IN A+ 3}
V+ 4
6 ^{IN B−} _{IN B+ 5}
5 ^{IN B+ IN B− 6}
OUT B 7
−^A+
+D−
B
C
(Top View)
14 OUT D OUT A 1
13 IN D− IN A− 2
12 IN D+ IN A+ 3
11 V−
V+ 4
10 IN C+ _{IN B+} 5
9 IN C−
IN B− 6
8 OUT C _{OUT B 7}
14 OUT D
−^A+
+D− ^{13 IN D−}
12 IN D+
11 V−
10 IN C+
9 IN C−
B
C
8 OUT C
(Top View)
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