LC75890W Datasheet, PDF (2/29 Pages) Sanyo Semicon Device – 1/4duty and Static Drive General-Purpose LCD Display Drivers

LC75890W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0V
Parameter
Symbol
Conditions
Maximum supply voltage
VDD max
VDD
Input voltage
Output voltage
VLCD max
VIN1
VIN2
VOUT
VLCD
CE, CL, DI, INH
OSCI : External clock operating mode
S1 to S37, COM1 to COM4, P1 to P12
Output current
Allowable power dissipation
IOUT1
IOUT2
IOUT3
Pd max
S1 to S36
COM1 to COM4, S37
P1 to P12 *1
Ta=85C
Operating temperature
Topr
Storage temperature
Tstg
Note : *1 The sum of output current through P1 to P12 must be 40mA or less.
Ratings
Unit
-0.3 to +4.2
V
-0.3 to +6.5
-0.3 to +4.2
V
-0.3 to VDD+0.3
-0.3 to VLCD+0.3
V
300
A
3
mA
5
100
mW
-40 to +85
C
-55 to +125
C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0V
Parameter
Supply voltage
Input high-level voltage
Input low-level voltage
External clock operating frequency
External clock duty cycle
Data setup time
Data hold time
Symbol
VDD
VLCD
VIH1
VIH2
VIL1
VIL2
fCK
DCK
tds
tdh
Conditions
VDD
VLCD: Internal oscillator operating mode
VLCD: External clock operating mode
CE, CL, DI, INH
OSCI: External clock operating mode
CE, CL, DI, INH
OSCI: External clock operating mode
OSCI: External clock operating mode [Figure 3]
OSCI: External clock operating mode [Figure 3]
CL, DI
[Figure 1][Figure 2]
CL, DI
[Figure 1][Figure 2]
Ratings
Unit
min
typ
max
2.7
3.6
2.7
5.5
V
VDD
0.7VDD
0.7VDD
0
0
10
5.5
3.6
V
VDD
0.2VDD
V
0.2VDD
38
600 kHz
30
50
70
%
160
ns
160
ns
CE wait time
tcp
CE, CL
[Figure 1][Figure 2]
160
ns
CE setup time
tcs
CE, CL
[Figure 1][Figure 2]
160
ns
CE hold time
tch
CE, CL
[Figure 1][Figure 2]
160
ns
High-level clock pulse width
tH
CL
[Figure 1][Figure 2]
160
ns
Low-level clock pulse width
tL
CL
[Figure 1][Figure 2]
160
ns
Rise time
Fall time
tr
CE, CL, DI
tf
CE, CL, DI
[Figure 1][Figure 2]
[Figure 1][Figure 2]
160
ns
160
ns
INH switching time
tc
INH
[Figure 4][Figure 5]
10
s
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