JLC1562B Datasheet, PDF (2/10 Pages) ON Semiconductor – I2C Bus I/O Expander

JLC1562B
Power−On
Reset
P7
SDA
P6
8 Bit
P5
SCL
P4
6 Bit
P3
V_DD
Latch
P2
P1
6−Bit
P0
DAC
A0
A1
1/2 V_CC
A2
3 Bit _Comp.
(C5−C7) ^A
5 Bit
5 Bit _Comp.
(C0−C4) ^B
NOTE: Internal Power On Reset sets P0 ~ P7 low, sets VDAC to 1/80 V_DD
and selects 1/2 V_DD for Comparator “B” threshold.
Figure 2. Block Diagram
V_DD
16 X R₆₅
R₆₄
Pin 1
VDAC
Comparator “B”
V_ref
R₆₃
R₄₀
R₃₉
R₂
R₁
GND
6:64 De−MUX (1 of 64 Decoder)
Bits D0 − D5 of Write Data (2)
V_ref Selector
Bit D6 of Write Data (2)
Write Data (2)
D6
1
0
V_ref Value
V_ref = VDAC
Vref
+
40
80
VDD
Write Data (2)
D5 D4 D3 D2 D1 D0
111111
•
•
•
•
1LSB +
1
80
VDD
0
0
0
0
0
1
000000
V_ref
64
80
VDD
•
•
•
•
2
80
VDD
1
80
VDD
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