CAV24C02 Datasheet, PDF (2/11 Pages) ON Semiconductor – 2-Kb, 4-Kb, 8-Kb and 16-Kb I2C CMOS Serial EEPROM

CAV24C02, CAV24C04, CAV24C08, CAV24C16
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
−65 to +150
°C
Voltage on any pin with respect to Ground (Note 1)
−0.5 to +6.5
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. During input transitions, voltage undershoot on any pin should not exceed −1 V for more than 20 ns. Voltage overshoot on pins A₀, A₁, A₂
and WP should not exceed V_CC + 1 V for more than 20 ns, while voltage on the I²C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of V_CC.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Symbol
Parameter
Min
Units
N_END (Note 3)
Endurance
1,000,000
Program / Erase Cycles
T_DR
Data Retention
100
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V_CC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
I_CCR
I_CCW
I_SB
I_L
V_IL
V_IH
Read Current
Write Current
Standby Current
I/O Pin Leakage
Input Low Voltage
Input High Voltage
Read, f_SCL = 400 kHz
Write, f_SCL = 400 kHz
All I/O Pins at GND or V_CC
Pin at GND or V_CC
T_A = −40°C to +125°C
A₀, A₁, A₂ and WP
SCL and SDA
V_OL
Output Low Voltage
V_CC > 2.5 V, I_OL = 3 mA
Min
−0.5
0.7 x V_CC
0.7 x V_CC
Max
1
2
5
2
0.3 x V_CC
V_CC + 0.5
5.5
0.4
Units
mA
mA
mA
mA
V
V
V
V
Table 4. PIN IMPEDANCE CHARACTERISTICS
(V_CC = 2.5 V to 5.5 V, T_A = −40°C to +125°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
C_IN (Note 4)
SDA Pin Capacitance
V_IN = 0 V, f = 1.0 MHz, V_CC = 5.0 V
8
pF
Other Pins
6
pF
I_WP (Note 5)
WP Input Current
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.6 V
130
mA
120
V_IN < V_IH, V_CC = 2.5 V
80
V_IN > V_IH
2
I_A (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H
V_IN < V_IH, V_CC = 5.5 V
V_IN < V_IH, V_CC = 3.6 V
50
mA
35
V_IN < V_IH, V_CC = 2.5 V
25
V_IN > V_IH
2
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x V_CC), the strong pull−down reverts to a weak current source.
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