CAT6219 Datasheet, PDF (2/9 Pages) Catalyst Semiconductor – 500mA CMOS LDO Regulator

CAT6219
V_IN
2.3 V
to 5.5 V
C_IN
1 mF
VIN VOUT
CAT6219
V_OUT
C_OUT
2.2 mF
V_IN
2.3 V
to 5.5 V
C_IN
1 mF
VIN VOUT
CAT6219
C_OUT
2.2 mF
V_OUT
R₁
OFF _ON
EN BYP
GND
C_BYP (Optional)
10 nF
OFF _ON
ǒ Ǔ V_OUT + 1.24 V
1
)
R₁
R₂
EN
ADJ
GND
R₂
Figure 1. Typical Application Circuit
Figure 2. Adjustable Output LDO
Table 1. PIN DESCRIPTIONS
Name
Function
VIN
Supply voltage input.
GND
Ground reference.
EN
Enable input (active high); a 2.5 MW pull−down
resistor is provided.
BYP
Optional bypass capacitor connection for noise
reduction and PSRR enhancing.
ADJ
Adjustable input. Feedback pin connected to
resistor divider.
VOUT
TAB
LDO Output Voltage.
To be connected to the ground plane on PCB
Pin Function
VIN is the supply pin for the LDO. A small 1 mF ceramic
bypass capacitor is required between the V_IN pin and ground
near the device. When using longer connections to the power
supply, C_IN value can be increased without limit. The
operating input voltage range is from 2.3 V to 5.5 V.
EN is the enable control logic (active high) for the regulator
output. It has a 2.5 MW pull−down resistor, which assures
that if EN pin is left open, the circuit is disabled.
VOUT is the LDO regulator output. A small 2.2 mF ceramic
bypass capacitor is required between the VOUT pin and
ground. For better transient response, its value can be
increased to 4.7 mF.
The capacitor should be located near the device. For the
SOT23-5 package, a continuous 500 mA output current may
turn-on the thermal protection. A 250 W internal shutdown
switch discharges the output capacitor in the no-load
condition.
GND is the ground reference for the LDO. The pin must be
connected to the ground plane on the PCB.
BYP is the reference bypass pin. An optional 0.01 mF
capacitor can be connected between BYP pin and GND to
reduce the output noise and enhance the PSRR at high
frequency.
ADJ is the adjustable input pin for the adjustable LDO. The
pin is connected to the resistor voltage divider.
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameter
Rating
Unit
V_IN
V_EN, V_OUT
Junction Temperature, T_J
Power Dissipation, P_D
Storage Temperature Range, T_S
Lead Temperature (soldering, 5 sec.)
0 to 6.5
V
−0.3 to V_IN + 0.3
V
+150
_C
Internally Limited (Note 1)
mW
−65 to +150
_C
260
_C
ESD Rating (Human Body Model)
3
kV
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
Table 3. RECOMMENDED OPERATING CONDITIONS (Note 2)
Parameter
Range
Unit
V_IN
2.3 to 5.5
V
V_EN
0 to V_IN
V
Junction Temperature Range, T_J
−40 to +125
_C
Package Thermal Resistance (SOT23−5), θ_JA
235
_C/W
NOTE: Typical application circuit with external components is shown above.
1. The maximum allowable power dissipation at any T_A (ambient temperature) is P_Dmax = (T_Jmax − T_A)/q_JA. Exceeding the maximum allowable
power dissipation will result in excessive die temperature, and the regulator will go into thermal shutdown.
2. The device is not guaranteed to work outside its operating rating.
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