CAT5241 Datasheet, PDF (2/16 Pages) Catalyst Semiconductor – Quad Digitally Programmable Potentiometers (DPP™) with 64 Taps and 2-wire Interface

CAT5241
PIN DESCRIPTION
Pin (SOIC)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
R_W0
R_L0
R_H0
A0
A2
R_W1
R_L1
R_H1
SDA
GND
R_H2
R_L2
R_W2
SCL
A3
A1
R_H3
R_L3
R_W3
V_CC
Function
Wiper Terminal for Potentiometer 0
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Device Address, LSB
Device Address
Wiper Terminal for Potentiometer 1
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Serial Data Input/Output
Ground
High Reference Terminal for Potentiometer 2
Low Reference Terminal for Potentiometer 2
Wiper Terminal for Potentiometer 2
Bus Serial Clock
Device Address
Device Address
High Reference Terminal for Potentiometer 3
Low Reference Terminal for Potentiometer 3
Wiper Terminal for Potentiometer 3
Supply Voltage
PIN DESCRIPTION
SCL: Serial Clock
The CAT5241 serial clock input pin is used to clock
all data transfers into or out of the device.
SDA: Serial Data
The CAT5241 bidirectional serial data pin is used to
transfer data into and out of the device. The SDA pin
is an open drain output and can be wire-or'd with the
other open drain or open collector outputs.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A match
in the slave address must be made with the address
input in order to initiate communication with the
CAT5241.
R_H, R_L: Resistor End Points
The four sets of R_H and R_L pins are equivalent to the
terminal connections on a mechanical potentiometer.
R_W: Wiper
The four R_W pins are equivalent to the wiper terminal
of a mechanical potentiometer.
DEVICE OPERATION
The CAT5241 is four resistor arrays integrated with I²C
serial interface logic, four 6-bit wiper control registers
and sixteen 6-bit, non-volatile memory data registers.
Each resistor array contains 63 separate resistive
elements connected in series. The physical ends of
each array are equivalent to the fixed terminals of a
mechanical potentiometer (R_H and R_L). R_H and R_L are
symmetrical and may be interchanged. The tap
positions between and at the ends of the series resis–
tors are connected to the output wiper terminals (R_W) by
a CMOS transistor switch. Only one tap point for each
potentiometer is connected to its wiper terminal at a
time and is determined by the value of the wiper control
register. Data can be read or written to the wiper control
registers or the non-volatile memory data registers via
the I²C bus. Additional instructions allow data to be
transferred between the wiper control registers and
each respective potentiometer's non-volatile data
registers. Also, the device can be instructed to operate
in an "increment/decrement" mode.
Doc. No. MD-2011 Rev. R
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice